trans4_16.vhd

来自「看了好多网了」· VHDL 代码 · 共 38 行

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity trans4_16 is
port(in4   : in  std_logic_vector(3 downto 0);
     out16 : out std_logic_vector(15 downto 0));
end trans4_16;

architecture trans_arch of trans4_16 is
begin
process(in4)
begin
case in4 is
      when "0000" => out16 <= "1111111111111110";
      when "0001" => out16 <= "1111111111111101";
      when "0010" => out16 <= "1111111111111011";
      when "0011" => out16 <= "1111111111110111";

      when "0100" => out16 <= "1111111111101111";

      when "0101" => out16 <= "1111111111011111";
      when "0110" => out16 <= "1111111110111111";
      when "0111" => out16 <= "1111111101111111";

      when "1000" => out16 <= "1111111011111111";
      when "1001" => out16 <= "1111110111111111";
      when "1010" => out16 <= "1111101111111111";
      when "1011" => out16 <= "1111011111111111";

      when "1100" => out16 <= "1110111111111111";
      when "1101" => out16 <= "1101111111111111";
      when "1110" => out16 <= "1011111111111111";
      when "1111" => out16 <= "0111111111111111";
      when others => out16 <= "1111111111111111";
end case;
end process;
end trans_arch;