dccount.map.qmsg

直流电机控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 13 13:26:21 2005 " "Info: Processing started: Sat Aug 13 13:26:21 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dccount -c dccount " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dccount -c dccount" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dccount.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dccount.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dccount-a " "Info: Found design unit 1: dccount-a" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dccount " "Info: Found entity 1: dccount" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dccount " "Info: Elaborating entity \"dccount\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ind_coil dccount.vhd(30) " "Info: (10035) Verilog HDL or VHDL information at dccount.vhd(30): object \"ind_coil\" declared but not used" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Hz dccount.vhd(60) " "Warning: VHDL Process Statement warning at dccount.vhd(60): signal \"Hz\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 60 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_MULTIPLE_PROCESS_SENSITIVITY_LISTS_PRESENT" "dccount.vhd(45) " "Error: VHDL Process Statement error at dccount.vhd(45): Process Statement cannot contain both a sensitivity list and a Wait Statement" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 45 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk dccount.vhd(50) " "Warning: VHDL Process Statement warning at dccount.vhd(50): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "dccount.vhd" "" { Text "D:/Quartus/dccount/dccount.vhd" 50 0 0 } }  } 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 2 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 2 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat Aug 13 13:26:25 2005 " "Error: Processing ended: Sat Aug 13 13:26:25 2005" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:04 " "Error: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}