step_motor.tan.qmsg

步进电机控制器,控制电机的VHDL源程序

{ "Info" "ITDB_TSU_RESULT" "\\process4:B d f 11.000 ns register " "Info: tsu for register \"\\process4:B\" (data pin = \"d\", clock pin = \"f\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns d 1 PIN PIN_33 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 2; PIN Node = 'd'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { d } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns \\process4:B 2 REG LC37 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC37; Fanout = 1; REG Node = '\\process4:B'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { d \process4:B } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "10.000 ns" { d \process4:B } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { d d~out \process4:B } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"f\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns \\process4:B 2 REG LC37 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 1; REG Node = '\\process4:B'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "0.000 ns" { f \process4:B } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f \process4:B } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out \process4:B } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "10.000 ns" { d \process4:B } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { d d~out \process4:B } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f \process4:B } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out \process4:B } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "f coil\[0\] t\[0\] 17.000 ns register " "Info: tco from clock \"f\" to destination pin \"coil\[0\]\" through register \"t\[0\]\" is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"f\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk_scan 2 REG LC4 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 9; REG Node = 'clk_scan'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "1.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns t\[0\] 3 REG LC65 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC65; Fanout = 1; REG Node = 't\[0\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { clk_scan t[0] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f clk_scan t[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out clk_scan t[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns t\[0\] 1 REG LC65 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC65; Fanout = 1; REG Node = 't\[0\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { t[0] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns coil\[0\] 2 PIN PIN_44 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_44; Fanout = 0; PIN Node = 'coil\[0\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "4.000 ns" { t[0] coil[0] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "4.000 ns" { t[0] coil[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { t[0] coil[0] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f clk_scan t[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out clk_scan t[0] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "4.000 ns" { t[0] coil[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.000 ns" { t[0] coil[0] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "comp\[11\] speed\[0\] f 6.000 ns register " "Info: th for register \"comp\[11\]\" (data pin = \"speed\[0\]\", clock pin = \"f\") is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"f\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns osc 2 REG LC66 13 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC66; Fanout = 13; REG Node = 'osc'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "1.000 ns" { f osc } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns comp\[11\] 3 REG LC36 51 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC36; Fanout = 51; REG Node = 'comp\[11\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { osc comp[11] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f osc comp[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out osc comp[11] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns speed\[0\] 1 PIN PIN_52 91 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 91; PIN Node = 'speed\[0\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { speed[0] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns comp\[11\] 2 REG LC36 51 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC36; Fanout = 51; REG Node = 'comp\[11\]'" {  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { speed[0] comp[11] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "10.000 ns" { speed[0] comp[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { speed[0] speed[0]~out comp[11] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f osc comp[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out osc comp[11] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "10.000 ns" { speed[0] comp[11] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { speed[0] speed[0]~out comp[11] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 13 13:15:56 2005 " "Info: Processing ended: Sat Aug 13 13:15:56 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}