📄 step_motor.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "f " "Info: Assuming node \"f\" is an undefined clock" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "f" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_scan " "Info: Detected ripple clock \"clk_scan\" as buffer" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_scan" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "osc " "Info: Detected ripple clock \"osc\" as buffer" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 21 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "osc" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "f register comp\[5\] register clk_scan 25.64 MHz 39.0 ns Internal " "Info: Clock \"f\" has Internal fmax of 25.64 MHz between source register \"comp\[5\]\" and destination register \"clk_scan\" (period= 39.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "25.000 ns + Longest register register " "Info: + Longest register to register delay is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns comp\[5\] 1 REG LC35 51 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 51; REG Node = 'comp\[5\]'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { comp[5] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 10.000 ns LessThan~867 2 COMB SEXP17 5 " "Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 10.000 ns; Loc. = SEXP17; Fanout = 5; COMB Node = 'LessThan~867'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "10.000 ns" { comp[5] LessThan~867 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 17.000 ns LessThan~877 3 COMB LC22 13 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 17.000 ns; Loc. = LC22; Fanout = 13; COMB Node = 'LessThan~877'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "7.000 ns" { LessThan~867 LessThan~877 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 25.000 ns clk_scan 4 REG LC4 9 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 25.000 ns; Loc. = LC4; Fanout = 9; REG Node = 'clk_scan'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { LessThan~877 clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 84.00 % " "Info: Total cell delay = 21.000 ns ( 84.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.00 % " "Info: Total interconnect delay = 4.000 ns ( 16.00 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "25.000 ns" { comp[5] LessThan~867 LessThan~877 clk_scan } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { comp[5] LessThan~867 LessThan~877 clk_scan } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 8.000ns 7.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.000 ns - Smallest " "Info: - Smallest clock skew is -9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"f\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clk_scan 2 REG LC4 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 9; REG Node = 'clk_scan'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "0.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out clk_scan } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f source 12.000 ns - Longest register " "Info: - Longest clock path from clock \"f\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns osc 2 REG LC66 13 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC66; Fanout = 13; REG Node = 'osc'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "1.000 ns" { f osc } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 21 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns comp\[5\] 3 REG LC35 51 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC35; Fanout = 51; REG Node = 'comp\[5\]'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { osc comp[5] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f osc comp[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out osc comp[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out clk_scan } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f osc comp[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out osc comp[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } } } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "25.000 ns" { comp[5] LessThan~867 LessThan~877 clk_scan } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { comp[5] LessThan~867 LessThan~877 clk_scan } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 8.000ns 7.000ns 6.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out clk_scan } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f osc comp[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out osc comp[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "f 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"f\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DIRECTION ind_coil\[3\] f 4.0 ns " "Info: Found hold time violation between source pin or register \"DIRECTION\" and destination pin or register \"ind_coil\[3\]\" for clock \"f\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"f\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk_scan 2 REG LC4 9 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC4; Fanout = 9; REG Node = 'clk_scan'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "1.000 ns" { f clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 17 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns ind_coil\[3\] 3 REG LC71 8 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC71; Fanout = 8; REG Node = 'ind_coil\[3\]'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { clk_scan ind_coil[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f clk_scan ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out clk_scan ind_coil[3] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 6.0ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f source 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"f\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns f 1 CLK PIN_83 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 24; CLK Node = 'f'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { f } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns DIRECTION 2 REG LC38 13 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 13; REG Node = 'DIRECTION'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "0.000 ns" { f DIRECTION } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f DIRECTION } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out DIRECTION } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f clk_scan ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out clk_scan ind_coil[3] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 6.0ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f DIRECTION } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out DIRECTION } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns - Shortest register register " "Info: - Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DIRECTION 1 REG LC38 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC38; Fanout = 13; REG Node = 'DIRECTION'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "" { DIRECTION } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns ind_coil\[3\] 2 REG LC71 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC71; Fanout = 8; REG Node = 'ind_coil\[3\]'" { } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { DIRECTION ind_coil[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { DIRECTION ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { DIRECTION ind_coil[3] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 16 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 18 -1 0 } } { "step_motor.vhd" "" { Text "D:/Quartus/step_motor/step_motor.vhd" 16 -1 0 } } } 0} } { { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "12.000 ns" { f clk_scan ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { f f~out clk_scan ind_coil[3] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 6.0ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "3.000 ns" { f DIRECTION } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { f f~out DIRECTION } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } { "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" "" { Report "D:/Quartus/step_motor/db/step_motor_cmp.qrpt" Compiler "step_motor" "UNKNOWN" "V1" "D:/Quartus/step_motor/db/step_motor.quartus_db" { Floorplan "D:/Quartus/step_motor/" "" "8.000 ns" { DIRECTION ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { DIRECTION ind_coil[3] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } } } 0}
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