buff8.map.qmsg

八位双向三态控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 12 14:58:44 2005 " "Info: Processing started: Fri Aug 12 14:58:44 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off buff8 -c buff8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buff8 -c buff8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buff8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file buff8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 buff8-buff8_arch " "Info: Found design unit 1: buff8-buff8_arch" {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 buff8 " "Info: Found entity 1: buff8" {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "buff8 " "Info: Elaborating entity \"buff8\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "bout buff8.vhd(21) " "Warning: VHDL Process Statement warning at buff8.vhd(21): signal \"bout\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 21 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "aout buff8.vhd(22) " "Warning: VHDL Process Statement warning at buff8.vhd(22): signal \"aout\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 22 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "bout buff8.vhd(12) " "Warning: VHDL Process Statement warning at buff8.vhd(12): signal or variable \"bout\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"bout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "aout buff8.vhd(12) " "Warning: VHDL Process Statement warning at buff8.vhd(12): signal or variable \"aout\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"aout\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "buff8.vhd" "" { Text "D:/Quartus/buff8/buff8.vhd" 12 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "39 " "Info: Implemented 39 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "0 " "Info: Implemented 0 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "18 " "Info: Implemented 18 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "2 " "Info: Implemented 2 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 12 14:58:50 2005 " "Info: Processing ended: Fri Aug 12 14:58:50 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}