buff8.map.eqn

八位双向三态控制

-- Copyright (C) 1991-2005 Altera Corporation
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--A1L35 is process0_193~10
A1L35_p1_out = A1L55 & !ncs & rd & !wr;
A1L35_p2_out = A1L35 & !ncs & !rd & wr;
A1L35_p3_out = A1L35 & !ncs & rd & !wr;
A1L35_or_out = A1L35_p1_out # A1L35_p2_out # A1L35_p3_out;
A1L35 = A1L35_or_out;


--A1L34 is bout[0]~66
A1L34_p0_out = A1L3 & wr;
A1L34_p1_out = A1L3 & ncs;
A1L34_p2_out = A1L34 & !ncs & rd & !wr;
A1L34_p3_out = A1L3 & A1L34;
A1L34_p4_out = A1L3 & !rd;
A1L34_or_out = A1L34_p0_out # A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;
A1L34 = A1L34_or_out;


--A1L25 is process0_67~10
A1L25_p1_out = !ncs & !rd & wr & A1L65;
A1L25_p2_out = A1L25 & !ncs & rd & !wr;
A1L25_p3_out = A1L25 & !ncs & !rd & wr;
A1L25_or_out = A1L25_p1_out # A1L25_p2_out # A1L25_p3_out;
A1L25 = A1L25_or_out;


--A1L44 is bout[1]~70
A1L44_p0_out = A1L5 & wr;
A1L44_p1_out = A1L5 & ncs;
A1L44_p2_out = A1L44 & !ncs & rd & !wr;
A1L44_p3_out = A1L5 & A1L44;
A1L44_p4_out = A1L5 & !rd;
A1L44_or_out = A1L44_p0_out # A1L44_p1_out # A1L44_p2_out # A1L44_p3_out # A1L44_p4_out;
A1L44 = A1L44_or_out;


--A1L54 is bout[2]~74
A1L54_p0_out = A1L7 & wr;
A1L54_p1_out = A1L7 & ncs;
A1L54_p2_out = A1L54 & !ncs & rd & !wr;
A1L54_p3_out = A1L7 & A1L54;
A1L54_p4_out = A1L7 & !rd;
A1L54_or_out = A1L54_p0_out # A1L54_p1_out # A1L54_p2_out # A1L54_p3_out # A1L54_p4_out;
A1L54 = A1L54_or_out;


--A1L64 is bout[3]~78
A1L64_p0_out = A1L9 & wr;
A1L64_p1_out = A1L9 & ncs;
A1L64_p2_out = A1L64 & !ncs & rd & !wr;
A1L64_p3_out = A1L9 & A1L64;
A1L64_p4_out = A1L9 & !rd;
A1L64_or_out = A1L64_p0_out # A1L64_p1_out # A1L64_p2_out # A1L64_p3_out # A1L64_p4_out;
A1L64 = A1L64_or_out;


--A1L74 is bout[4]~82
A1L74_p0_out = A1L11 & wr;
A1L74_p1_out = A1L11 & ncs;
A1L74_p2_out = A1L74 & !ncs & rd & !wr;
A1L74_p3_out = A1L11 & A1L74;
A1L74_p4_out = A1L11 & !rd;
A1L74_or_out = A1L74_p0_out # A1L74_p1_out # A1L74_p2_out # A1L74_p3_out # A1L74_p4_out;
A1L74 = A1L74_or_out;


--A1L84 is bout[5]~86
A1L84_p0_out = A1L31 & wr;
A1L84_p1_out = A1L31 & ncs;
A1L84_p2_out = A1L84 & !ncs & rd & !wr;
A1L84_p3_out = A1L31 & A1L84;
A1L84_p4_out = A1L31 & !rd;
A1L84_or_out = A1L84_p0_out # A1L84_p1_out # A1L84_p2_out # A1L84_p3_out # A1L84_p4_out;
A1L84 = A1L84_or_out;


--A1L94 is bout[6]~90
A1L94_p0_out = A1L51 & wr;
A1L94_p1_out = A1L51 & ncs;
A1L94_p2_out = A1L94 & !ncs & rd & !wr;
A1L94_p3_out = A1L51 & A1L94;
A1L94_p4_out = A1L51 & !rd;
A1L94_or_out = A1L94_p0_out # A1L94_p1_out # A1L94_p2_out # A1L94_p3_out # A1L94_p4_out;
A1L94 = A1L94_or_out;


--A1L05 is bout[7]~94
A1L05_p0_out = A1L71 & wr;
A1L05_p1_out = A1L71 & ncs;
A1L05_p2_out = A1L05 & !ncs & rd & !wr;
A1L05_p3_out = A1L71 & A1L05;
A1L05_p4_out = A1L71 & !rd;
A1L05_or_out = A1L05_p0_out # A1L05_p1_out # A1L05_p2_out # A1L05_p3_out # A1L05_p4_out;
A1L05 = A1L05_or_out;


--A1L81 is aout[0]~66
A1L81_p0_out = A1L82 & !wr;
A1L81_p1_out = A1L82 & ncs;
A1L81_p2_out = A1L81 & !ncs & !rd & wr;
A1L81_p3_out = A1L82 & A1L81;
A1L81_p4_out = A1L82 & rd;
A1L81_or_out = A1L81_p0_out # A1L81_p1_out # A1L81_p2_out # A1L81_p3_out # A1L81_p4_out;
A1L81 = A1L81_or_out;


--A1L91 is aout[1]~70
A1L91_p0_out = A1L03 & !wr;
A1L91_p1_out = A1L03 & ncs;
A1L91_p2_out = A1L91 & !ncs & !rd & wr;
A1L91_p3_out = A1L03 & A1L91;
A1L91_p4_out = A1L03 & rd;
A1L91_or_out = A1L91_p0_out # A1L91_p1_out # A1L91_p2_out # A1L91_p3_out # A1L91_p4_out;
A1L91 = A1L91_or_out;


--A1L02 is aout[2]~74
A1L02_p0_out = A1L23 & !wr;
A1L02_p1_out = A1L23 & ncs;
A1L02_p2_out = A1L02 & !ncs & !rd & wr;
A1L02_p3_out = A1L23 & A1L02;
A1L02_p4_out = A1L23 & rd;
A1L02_or_out = A1L02_p0_out # A1L02_p1_out # A1L02_p2_out # A1L02_p3_out # A1L02_p4_out;
A1L02 = A1L02_or_out;


--A1L12 is aout[3]~78
A1L12_p0_out = A1L43 & !wr;
A1L12_p1_out = A1L43 & ncs;
A1L12_p2_out = A1L12 & !ncs & !rd & wr;
A1L12_p3_out = A1L43 & A1L12;
A1L12_p4_out = A1L43 & rd;
A1L12_or_out = A1L12_p0_out # A1L12_p1_out # A1L12_p2_out # A1L12_p3_out # A1L12_p4_out;
A1L12 = A1L12_or_out;


--A1L22 is aout[4]~82
A1L22_p0_out = A1L63 & !wr;
A1L22_p1_out = A1L63 & ncs;
A1L22_p2_out = A1L22 & !ncs & !rd & wr;
A1L22_p3_out = A1L63 & A1L22;
A1L22_p4_out = A1L63 & rd;
A1L22_or_out = A1L22_p0_out # A1L22_p1_out # A1L22_p2_out # A1L22_p3_out # A1L22_p4_out;
A1L22 = A1L22_or_out;


--A1L32 is aout[5]~86
A1L32_p0_out = A1L83 & !wr;
A1L32_p1_out = A1L83 & ncs;
A1L32_p2_out = A1L32 & !ncs & !rd & wr;
A1L32_p3_out = A1L83 & A1L32;
A1L32_p4_out = A1L83 & rd;
A1L32_or_out = A1L32_p0_out # A1L32_p1_out # A1L32_p2_out # A1L32_p3_out # A1L32_p4_out;
A1L32 = A1L32_or_out;


--A1L42 is aout[6]~90
A1L42_p0_out = A1L04 & !wr;
A1L42_p1_out = A1L04 & ncs;
A1L42_p2_out = A1L42 & !ncs & !rd & wr;
A1L42_p3_out = A1L04 & A1L42;
A1L42_p4_out = A1L04 & rd;
A1L42_or_out = A1L42_p0_out # A1L42_p1_out # A1L42_p2_out # A1L42_p3_out # A1L42_p4_out;
A1L42 = A1L42_or_out;


--A1L52 is aout[7]~94
A1L52_p0_out = A1L24 & !wr;
A1L52_p1_out = A1L24 & ncs;
A1L52_p2_out = A1L52 & !ncs & !rd & wr;
A1L52_p3_out = A1L24 & A1L52;
A1L52_p4_out = A1L24 & rd;
A1L52_or_out = A1L52_p0_out # A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = A1L52_or_out;


--A1L55 is reduce_nor~22sexp
A1L55 = EXP(!ncs & !rd & wr);


--A1L65 is reduce_nor~23sexp
A1L65 = EXP(!ncs & rd & !wr);


--ncs is ncs
--operation mode is input

ncs = INPUT();


--rd is rd
--operation mode is input

rd = INPUT();


--wr is wr
--operation mode is input

wr = INPUT();


--A1L82 is b[0]~7
--operation mode is bidir

A1L82 = b[0];

--b[0] is b[0]
--operation mode is bidir

b[0]_tri_out = TRI(A1L34, A1L25);
b[0] = BIDIR(b[0]_tri_out);


--A1L03 is b[1]~6
--operation mode is bidir

A1L03 = b[1];

--b[1] is b[1]
--operation mode is bidir

b[1]_tri_out = TRI(A1L44, A1L25);
b[1] = BIDIR(b[1]_tri_out);


--A1L23 is b[2]~5
--operation mode is bidir

A1L23 = b[2];

--b[2] is b[2]
--operation mode is bidir

b[2]_tri_out = TRI(A1L54, A1L25);
b[2] = BIDIR(b[2]_tri_out);


--A1L43 is b[3]~4
--operation mode is bidir

A1L43 = b[3];

--b[3] is b[3]
--operation mode is bidir

b[3]_tri_out = TRI(A1L64, A1L25);
b[3] = BIDIR(b[3]_tri_out);


--A1L63 is b[4]~3
--operation mode is bidir

A1L63 = b[4];

--b[4] is b[4]
--operation mode is bidir

b[4]_tri_out = TRI(A1L74, A1L25);
b[4] = BIDIR(b[4]_tri_out);


--A1L83 is b[5]~2
--operation mode is bidir

A1L83 = b[5];

--b[5] is b[5]
--operation mode is bidir

b[5]_tri_out = TRI(A1L84, A1L25);
b[5] = BIDIR(b[5]_tri_out);


--A1L04 is b[6]~1
--operation mode is bidir

A1L04 = b[6];

--b[6] is b[6]
--operation mode is bidir

b[6]_tri_out = TRI(A1L94, A1L25);
b[6] = BIDIR(b[6]_tri_out);


--A1L24 is b[7]~0
--operation mode is bidir

A1L24 = b[7];

--b[7] is b[7]
--operation mode is bidir

b[7]_tri_out = TRI(A1L05, A1L25);
b[7] = BIDIR(b[7]_tri_out);


--A1L3 is a[0]~7
--operation mode is bidir

A1L3 = a[0];

--a[0] is a[0]
--operation mode is bidir

a[0]_tri_out = TRI(A1L81, A1L35);
a[0] = BIDIR(a[0]_tri_out);


--A1L5 is a[1]~6
--operation mode is bidir

A1L5 = a[1];

--a[1] is a[1]
--operation mode is bidir

a[1]_tri_out = TRI(A1L91, A1L35);
a[1] = BIDIR(a[1]_tri_out);


--A1L7 is a[2]~5
--operation mode is bidir

A1L7 = a[2];

--a[2] is a[2]
--operation mode is bidir

a[2]_tri_out = TRI(A1L02, A1L35);
a[2] = BIDIR(a[2]_tri_out);


--A1L9 is a[3]~4
--operation mode is bidir

A1L9 = a[3];

--a[3] is a[3]
--operation mode is bidir

a[3]_tri_out = TRI(A1L12, A1L35);
a[3] = BIDIR(a[3]_tri_out);


--A1L11 is a[4]~3
--operation mode is bidir

A1L11 = a[4];

--a[4] is a[4]
--operation mode is bidir

a[4]_tri_out = TRI(A1L22, A1L35);
a[4] = BIDIR(a[4]_tri_out);


--A1L31 is a[5]~2
--operation mode is bidir

A1L31 = a[5];

--a[5] is a[5]
--operation mode is bidir

a[5]_tri_out = TRI(A1L32, A1L35);
a[5] = BIDIR(a[5]_tri_out);


--A1L51 is a[6]~1
--operation mode is bidir

A1L51 = a[6];

--a[6] is a[6]
--operation mode is bidir

a[6]_tri_out = TRI(A1L42, A1L35);
a[6] = BIDIR(a[6]_tri_out);


--A1L71 is a[7]~0
--operation mode is bidir

A1L71 = a[7];

--a[7] is a[7]
--operation mode is bidir

a[7]_tri_out = TRI(A1L52, A1L35);
a[7] = BIDIR(a[7]_tri_out);