📄 buff8.map.rpt
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Analysis & Synthesis report for buff8
Fri Aug 12 14:58:50 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Aug 12 14:58:50 2005 ;
; Quartus II Version ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name ; buff8 ;
; Top-level Entity Name ; buff8 ;
; Family ; MAX7000S ;
; Total macrocells ; 18 ;
; Total pins ; 19 ;
+-----------------------------+-----------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; buff8 ; buff8 ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+----------------------------------------------------------------------+-----------------+---------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------+
; buff8.vhd ; yes ; User VHDL File ; D:/Quartus/buff8/buff8.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 18 ;
; Total registers ; 0 ;
; I/O pins ; 19 ;
; Shareable expanders ; 2 ;
; Maximum fan-out node ; ncs ;
; Maximum fan-out ; 20 ;
; Total fan-out ; 128 ;
; Average fan-out ; 3.28 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |buff8 ; 18 ; 19 ; |buff8 ;
+----------------------------+------------+------+---------------------+
+----------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+----+
; Latch Name ; ;
+-----------------------------------------------+----+
; aout[0] ; ;
; process0_193 ; ;
; aout[1] ; ;
; aout[2] ; ;
; aout[3] ; ;
; aout[4] ; ;
; aout[5] ; ;
; aout[6] ; ;
; aout[7] ; ;
; bout[0] ; ;
; process0_67 ; ;
; bout[1] ; ;
; bout[2] ; ;
; bout[3] ; ;
; bout[4] ; ;
; bout[5] ; ;
; bout[6] ; ;
; bout[7] ; ;
; Number of user-specified and inferred latches ; 18 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Quartus/buff8/buff8.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Fri Aug 12 14:58:44 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off buff8 -c buff8
Info: Found 2 design units, including 1 entities, in source file buff8.vhd
Info: Found design unit 1: buff8-buff8_arch
Info: Found entity 1: buff8
Info: Elaborating entity "buff8" for the top level hierarchy
Warning: VHDL Process Statement warning at buff8.vhd(21): signal "bout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at buff8.vhd(22): signal "aout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at buff8.vhd(12): signal or variable "bout" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "bout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at buff8.vhd(12): signal or variable "aout" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "aout" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Implemented 39 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 0 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 18 macrocells
Info: Implemented 2 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Processing ended: Fri Aug 12 14:58:50 2005
Info: Elapsed time: 00:00:07
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