wreg516.h

keil C51 LCD 驱动源码,其中还有I2C驱动,ADC驱动,键盘操作等,是一个完整的keil源代码,供大家参考

/****************************************************************************
   +----------------------------------------------------------------------+
   | Copyright Trumpion Microelectronics Inc. 1999                        |
   | Trumpion Microelectronics Inc. reserves the right to change products |
   | or specifications without notice.                                    |
   +----------------------------------------------------------------------+
   Project    : LCD monitor
   Version    : 0.94
   File Name  : wreg516.h
   Functions  : general and special register definition for W78E516
   Revision   :

   1999-05-18  OriginalTeam    First Created
****************************************************************************/

#ifndef _WREG516_H
#define _WREG516_H

/*  BYTE Registers  */
sfr    P0    = 0x80;
sfr    P1    = 0x90;
sfr    P2    = 0xA0;
sfr    P3    = 0xB0;
sfr    PSW   = 0xD0;
sfr    ACC   = 0xE0;
sfr    B     = 0xF0;
sfr    SP    = 0x81;
sfr    DPL   = 0x82;
sfr    DPH   = 0x83;
sfr    PCON  = 0x87;
sfr    TCON  = 0x88;
sfr    TMOD  = 0x89;
sfr    TL0   = 0x8A;
sfr    TL1   = 0x8B;
sfr    TH0   = 0x8C;
sfr    TH1   = 0x8D;
sfr    IE    = 0xA8;
sfr    IP    = 0xB8;
sfr    SCON  = 0x98;
sfr    SBUF  = 0x99;

/*  8052 Extensions  */
sfr    T2CON  = 0xC8;
sfr    RCAP2L = 0xCA;
sfr    RCAP2H = 0xCB;
sfr    TL2    = 0xCC;
sfr    TH2    = 0xCD;

/*  BIT Registers  */
/*  PSW  */
sbit    CY    = 0xD7;
sbit    AC    = 0xD6;
sbit    F0    = 0xD5;
sbit    RS1   = 0xD4;
sbit    RS0   = 0xD3;
sbit    OV    = 0xD2;
sbit    P     = 0xD0;

/*  TCON  */
sbit    TF1   = 0x8F;
sbit    TR1   = 0x8E;
sbit    TF0   = 0x8D;
sbit    TR0   = 0x8C;
sbit    IE1   = 0x8B;
sbit    IT1   = 0x8A;
sbit    IE0   = 0x89;
sbit    IT0   = 0x88;

/*  IE  */
sbit    EA    = 0xAF;
sbit    ES    = 0xAC;
sbit    ET1   = 0xAB;
sbit    EX1   = 0xAA;
sbit    ET0   = 0xA9;
sbit    EX0   = 0xA8;

/*  IP  */
sbit    PS    = 0xBC;
sbit    PT1   = 0xBB;
sbit    PX1   = 0xBA;
sbit    PT0   = 0xB9;
sbit    PX0   = 0xB8;

/*  P3  */
sbit    RD    = 0xB7;
sbit    WR    = 0xB6;
sbit    T1    = 0xB5;
sbit    T0    = 0xB4;
sbit    INT1  = 0xB3;
sbit    INT0  = 0xB2;
sbit    TXD   = 0xB1;
sbit    RXD   = 0xB0;

/*  SCON  */
sbit    SM0   = 0x9F;
sbit    SM1   = 0x9E;
sbit    SM2   = 0x9D;
sbit    REN   = 0x9C;
sbit    TB8   = 0x9B;
sbit    RB8   = 0x9A;
sbit    TI    = 0x99;
sbit    RI    = 0x98;

/*  8052 Extensions  */
/*  IE  */
sbit    ET2   = 0xAD;

/*  IP  */
sbit    PT2   = 0xBD;

/*  P1  */
sbit    T2EX  = 0x91;
sbit    T2    = 0x90;
             
/*  T2CON  */
sbit    TF2   = 0xCF;
sbit    EXF2  = 0xCE;
sbit    RCLK  = 0xCD;
sbit    TCLK  = 0xCC;
sbit    EXEN2 = 0xCB;
sbit    TR2   = 0xCA;
sbit    C_T2  = 0xC9;
sbit    CP_RL2= 0xC8;

/*  Extension for W78E516 */
sfr     CHPCON  = 0xBF;
sfr     SFRAL   = 0xC4;
sfr     SFRAH   = 0xC5;
sfr     SFRFD   = 0xC6;
sfr     SFRCN   = 0xC7;
sfr     P4      = 0xD8;
sfr     CHPENR  = 0xF6;

/*  Extension for SM2965 */ 
sfr     IMPSR   = 0x85;       // Internal Memory Page Select Register
sfr     SCONF   = 0xBF;       // System Control Register
sfr     WDTC    = 0x9F;       // Watch Dog Timer Control Register
sfr     FCR     = 0xF7;       // Flash Control Register
sfr     FAH     = 0xF4;       // Flash Address-High Register
sfr     FAL     = 0xF5;       // Flash Address-Low  Register
sfr     FDAT    = 0xF6;       // Flash Data  Register


sbit    P0_0    = P0 ^ 0;
sbit    P0_1    = P0 ^ 1;
sbit    P0_2    = P0 ^ 2;
sbit    P0_3    = P0 ^ 3;
sbit    P0_4    = P0 ^ 4;
sbit    P0_5    = P0 ^ 5;
sbit    P0_6    = P0 ^ 6;
sbit    P0_7    = P0 ^ 7;

sbit    P1_0    = P1 ^ 0;
sbit    P1_1    = P1 ^ 1;
sbit    P1_2    = P1 ^ 2;
sbit    P1_3    = P1 ^ 3;
sbit    P1_4    = P1 ^ 4;
sbit    P1_5    = P1 ^ 5;
sbit    P1_6    = P1 ^ 6;
sbit    P1_7    = P1 ^ 7;

sbit    P2_0    = P2 ^ 0;
sbit    P2_1    = P2 ^ 1;
sbit    P2_2    = P2 ^ 2;
sbit    P2_3    = P2 ^ 3;
sbit    P2_4    = P2 ^ 4;
sbit    P2_5    = P2 ^ 5;
sbit    P2_6    = P2 ^ 6;
sbit    P2_7    = P2 ^ 7;

sbit    P3_0    = P3 ^ 0;
sbit    P3_1    = P3 ^ 1;
sbit    P3_2    = P3 ^ 2;
sbit    P3_3    = P3 ^ 3;
sbit    P3_4    = P3 ^ 4;
sbit    P3_5    = P3 ^ 5;
sbit    P3_6    = P3 ^ 6;
sbit    P3_7    = P3 ^ 7;

sbit    P4_0    = P4 ^ 0;
sbit    P4_1    = P4 ^ 1;
sbit    P4_2    = P4 ^ 2;
sbit    P4_3    = P4 ^ 3;

//sbit    CEN      = SFRCN ^ 4;
//sbit    OEN      = SFRCN ^ 5;
//sbit    WFWIN    = SFRCN ^ 6;

//sbit    FPROGEN  = CHPCON ^ 0;
//sbit    FBOOTSL  = CHPCON ^ 1;
//sbit    ENAUXRAM = CHPCON ^ 4;
//sbit    SWRESET  = CHPCON ^ 7;

#endif