wave.vhd

VHDL小程序（本人的一些小成绩哦

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL ;
USE work.waveform_pkg.all ;

entity wave is
      port (
            clock : in  std_logic ;
            reset : in  boolean ;
            waves : out rom_word
           ) ;
end wave;

architecture rtl of wave is 
    signal step,next_step : rom_range ;
    signal delay          : data_word  ;
  begin

  next_step <= rom_range'high when step = rom_range'high else step + 1 ;

   time_step : process
     begin
       wait until clock'event and clock = '1' and clock'last_value = '0';
       if (reset) then
         step <= 0 ;
       elsif (delay = 1) then 
         step <= next_step ;
       else
         null ;
       end if ;
   end process ;

   delay_step : process
     begin
       wait until clock'event and clock = '1' ;
       if (reset) then
         delay <= data(0) ;
       elsif (delay = 1) then 
         delay <= data(next_step) ;
       else
         delay <= delay - 1 ;
       end if ;
    end process ;

   waves <= rom_data(step) ;

end rtl;