ab.vhd

VHDL小程序（本人的一些小成绩哦

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ab is
  port (  CLK,CLR: IN STD_LOGIC;
          DD     : in std_logic_vector(1 downto 0);
          LD     : IN STD_LOGIC_VECTOR(17 DOWNTO 0); 
       OUT1,OUT2 : out INTEGER RANGE 0 TO 255;
         OUT3    : out std_logic_vector(7 downto 0)
       );
end ab;

architecture Behav of ab is
  component FANG
    PORT(CLK:IN STD_LOGIC; 
         CLR:IN INTEGER RANGE 0 TO 1;
         Q:OUT INTEGER RANGE 0 TO 255);
  END COMPONENT;
  COMPONENT FENPIN    
      Port (clr,clk:in std_logic;
                 LD: IN STD_LOGIC_VECTOR( 17 DOWNTO 0 );
               clk1:out std_logic);
  END COMPONENT;
  COMPONENT SANJIAO
    PORT(CLK:IN STD_LOGIC;
         CLR:IN INTEGER RANGE 0 TO 1;
          Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT;
  COMPONENT SIN
    PORT(CLK:IN STD_LOGIC;
         CLR:IN INTEGER RANGE 0 TO 1;
         d:OUT INTEGER RANGE 0 TO 255);
  END COMPONENT;
  COMPONENT YIMA
    PORT (IN1  : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
         OUT11,OUT22,OUT33 : OUT INTEGER RANGE 0 TO 1   );
  END COMPONENT;
  SIGNAL      CLKOUT  : STD_LOGIC;
  SIGNAL    S1,S2,S3  : INTEGER RANGE 0 TO 1;
  SIGNAL        QQ1   :  std_logic_vector(7 downto 0);
BEGIN

  U0 : YIMA    PORT MAP (DD,S1,S2,S3);
  U1 : FENPIN  PORT MAP (clr,clk,LD,CLKOUT);
  U2 : FANG    PORT MAP (CLKOUT,S1,OUT1);
  U3 : SANJIAO PORT MAP (CLKOUT,S2,OUT3);
  U4 : SIN     PORT MAP (CLKOUT,S3,OUT2);
END Behav ;

library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity FENPIN is
      Port (clr,clk:in std_logic;
            LD: IN STD_LOGIC_VECTOR( 17 DOWNTO 0 );
            clk1:out std_logic);
  end FENPIN;
   architecture Behavioral of FENPIN is
   signal cnt:STD_LOGIC_VECTOR(17 DOWNTO 0);
    signal sclk1:std_logic;
   begin
  clk1<=sclk1;
     process(clr,clk)
   begin 
      if clr='1' then
        cnt<="000000000000000000";   
      sclk1<='0';
    elsif(clk'event and clk='1') then
       if cnt=LD then
       sclk1<=not sclk1;
       cnt<="000000000000000000";
       else
       cnt<=cnt+1;
         end if;
     end if;
    end process  ;
  end Behavioral;
CONFIGURATION con1 OF FENPIN IS
FOR Behavioral
END  FOR;
END CON1;