arictl.vhd

8位相 加乘法器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ARICTL IS
    PORT (
        CLK : IN STD_LOGIC;
        START : IN STD_LOGIC;
        CLKOUT : OUT STD_LOGIC;
        RSTALL : OUT STD_LOGIC;
        ARIEND : OUT STD_LOGIC
    );
END ARICTL;

ARCHITECTURE behav OF ARICTL IS
    SIGNAL CNT4B : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
    PROCESS(CLK, START)
    BEGIN
        RSTALL <= START;
        IF START = '1' THEN
            CNT4B <= "0000";
        ELSIF CLK'EVENT AND CLK  = '1' THEN
            IF CNT4B < 8 THEN
                CNT4B <= CNT4B + 1;
            END IF;
        END IF;
    END PROCESS;
    PROCESS(CLK, CNT4B, START)
    BEGIN
        IF START = '0' THEN
            IF CNT4B < 8 THEN
                CLKOUT <= CLK;
                ARIEND <= '0';
            ELSE
                CLKOUT <= '0';
                ARIEND <= '1';
            END IF;
        ELSE
            CLKOUT <= CLK;
            ARIEND <= '0';
        END IF;
    END PROCESS;
END behav;