verilog.log

来自「8051的Verilog」· LOG 代码 · 共 296 行 · 第 1/2 页

Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_pc.v"
Compiling source file "../../../rtl/verilog/oc8051_reg8.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_reg8.v", 48: 
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_reg8.v"
Compiling source file "../../../rtl/verilog/oc8051_reg2.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_reg2.v"
Compiling source file "../../../rtl/verilog/oc8051_reg1.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_reg1.v"
Compiling source file "../../../rtl/verilog/oc8051_reg4.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_reg4.v"
Compiling source file "../../../rtl/verilog/oc8051_ram_wr_sel.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_ram_wr_sel.v", 48: 
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_wr_sel.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_ram_wr_sel.v", 51: 
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_wr_sel.v"
Compiling source file "../../../rtl/verilog/oc8051_ram_rd_sel.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_ram_rd_sel.v", 48: 
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_rd_sel.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_ram_rd_sel.v", 51: 
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_rd_sel.v"
Compiling source file "../../../rtl/verilog/oc8051_ram_top.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_top.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_top.v"
Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_ram.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_ram.v"
Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_xram.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_xram.v"
Compiling source file "../../../rtl/verilog/oc8051_acc.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_acc.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_acc.v"
Compiling source file "../../../rtl/verilog/oc8051_comp.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_comp.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_comp.v"
Compiling source file "../../../rtl/verilog/oc8051_sp.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_sp.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_sp.v"
Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../sim/rtl_sim/src/verilog/oc8051_uart_test.v"
Compiling source file "../../../sim/rtl_sim/src/verilog/oc8051_rom.v"
Compiling source file "../../../rtl/verilog/oc8051_dptr.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_dptr.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_dptr.v"
Compiling source file "../../../rtl/verilog/oc8051_cy_select.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_cy_select.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_cy_select.v"
Compiling source file "../../../rtl/verilog/oc8051_psw.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_psw.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_psw.v"
Compiling source file "../../../rtl/verilog/oc8051_indi_addr.v"

Warning!  Code following `include command is ignored        [Verilog-CAICI]    
          "../../../rtl/verilog/oc8051_indi_addr.v", 49: 
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_indi_addr.v"
Compiling source file "../../../rtl/verilog/oc8051_rom_addr_sel.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_rom_addr_sel.v"
Compiling source file "../../../rtl/verilog/oc8051_ext_addr_sel.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ext_addr_sel.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ext_addr_sel.v"
Compiling source file "../../../rtl/verilog/oc8051_reg3.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_reg3.v"
Compiling source file "../../../rtl/verilog/oc8051_ram_sel.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_sel.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ram_sel.v"
Compiling source file "../../../rtl/verilog/oc8051_ports.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ports.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_ports.v"
Compiling source file "../../../rtl/verilog/oc8051_b_register.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_b_register.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_b_register.v"
Compiling source file "../../../rtl/verilog/oc8051_uart.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_uart.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_uart.v"
Compiling source file "../../../rtl/verilog/oc8051_int.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_int.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_int.v"
Compiling source file "../../../rtl/verilog/oc8051_tc.v"
Compiling included source file "oc8051_defines.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_tc.v"
Compiling included source file "oc8051_timescale.v"
Continuing compilation of source file "../../../rtl/verilog/oc8051_tc.v"
Highest level modules:
oc8051_tb

time                    1 step           0: pass
time                  186 step           1: pass
time                  306 step           2: pass
time                  426 step           3: pass
time                  546 step           4: pass
time                  656 step           5: pass

 Done!
L155 "../../../bench/verilog/oc8051_tb.v": $finish at simulation time 65600
14 warnings
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.3 secs to compile + 0.1 secs to link + 0.1 secs in simulation
End of VERILOG-XL 3.30.p001   Aug  3, 2001  12:27:19