r_bank.hex

8051的Verilog

00_60] = 8'h75;
    buff [16'h00_61] = 8'h80;
    buff [16'h00_62] = 8'h04;
end

always @(posedge clk)
begin
  data1 <= #1 buff [addr];
  data2 <= #1 buff [addr+1];
  data3 <= #1 buff [addr+2];
end

endmodule