ledall.vhd

大屏幕led点阵显示的驱动时序。 使用vhdl语言描述。其中rom文件可以使用lpm_megcore自动生成。

--元件例化
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
		
entity ledall is
port(clkin :in std_logic;
     outera:out std_logic_vector(15 downto 0);
     outerb:out std_logic_vector(3 downto 0));  
end ledall;
architecture beh of ledall is

component pin
port(f1m  :in std_logic;
     f800 :out std_logic);
end component;

component source1
port(clk  :in std_logic;
     outer:out std_logic_vector(7 downto 0));
end component;

component source2
port(clk  :in std_logic;
     iner :in std_logic_vector(3 downto 0);
     outer:out std_logic_vector(3 downto 0));
end component;

component rom1
port(address:in  STD_LOGIC_VECTOR (7 DOWNTO 0);
	 inclock:in  STD_LOGIC ;
	 q      :out STD_LOGIC_VECTOR (15 DOWNTO 0));
end component;
signal sig0,sig1,sig2:std_logic;
signal temp:std_logic_vector(7 downto 0);
begin 
sig1<=not sig0;sig2<=not sig0;

U1:source1 port map(sig0,temp(7 downto 0));
U2:source2 port map(sig1,temp(3 downto 0),outerb(3 downto 0));
U3:rom1    port map(temp(7 downto 0),sig2,outera(15 downto 0));
U4:pin     port map(clkin,sig0);
end beh;