📄 pin.vhd
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--分频程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pin is
port(f1m:in std_logic;
f800:out std_logic);
end pin;
architecture behave of pin is
signal Count : integer range 0 to 999;
begin
DivideCLK :
process(f1m)--对1M的信号1000分频 1KHz
begin
if (f1m'event and f1m = '1')then
if Count<499 then f800<='0';Count<=Count+1;
elsif Count<999 then f800<= '1';Count <= Count+1;
elsif Count>=999 then f800<='0';Count<=0;
end if;
end if;
end process;
end behave;
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