fdiv.vhd

电子密码锁的vhdl编程实现

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fdiv is
  port(
       clk:   IN std_logic; -- 确认输入

       divout: out std_logic   
      );
end entity fdiv;

architecture behv of fdiv is
--signal 声明
 signal d : std_logic_vector(3 downto 0);
 signal o : std_logic; 
begin
 process(clk)
  begin
  if clk'event and clk = '1' then 
   if d = "1001" then d <= "0000"; o <= not o;
     else d <= d + '1';
     end if;
   divout <= o;
   end if;
 end process;
 
end behv;