sin_rom.tan.qmsg

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

{ "Info" "ITAN_NO_REG2REG_EXIST" "inclock " "Info: No valid register-to-register data paths exist for clock \"inclock\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6 address\[6\] inclock 7.500 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6\" (data pin = \"address\[6\]\", clock pin = \"inclock\") is 7.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns address\[6\] 1 PIN PIN_69 8 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_69; Fanout = 8; PIN Node = 'address\[6\]'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { address[6] } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(0.800 ns) 8.700 ns altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6 2 MEM EC9_A 1 " "Info: 2: + IC(3.000 ns) + CELL(0.800 ns) = 8.700 ns; Loc. = EC9_A; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "3.800 ns" { address[6] altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 65.52 % " "Info: Total cell delay = 5.700 ns ( 65.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 34.48 % " "Info: Total interconnect delay = 3.000 ns ( 34.48 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "8.700 ns" { address[6] altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { address[6] address[6]~out altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } { 0.000ns 0.000ns 3.000ns } { 0.000ns 4.900ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.200 ns + " "Info: + Micro setup delay of destination is 1.200 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.400 ns - Shortest memory " "Info: - Shortest clock path from clock \"inclock\" to destination memory is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_55 80 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 80; CLK Node = 'inclock'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { inclock } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6 2 MEM EC9_A 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC9_A; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[2\]~reg_ra6'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "0.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "8.700 ns" { address[6] altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.700 ns" { address[6] address[6]~out altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } { 0.000ns 0.000ns 3.000ns } { 0.000ns 4.900ns 0.800ns } } } { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[2]~reg_ra6 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclock q\[7\] altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0 18.600 ns memory " "Info: tco from clock \"inclock\" to destination pin \"q\[7\]\" through memory \"altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0\" is 18.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 2.400 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to source memory is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_55 80 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 80; CLK Node = 'inclock'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { inclock } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0 2 MEM EC10_C 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC10_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "0.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.800 ns + Longest memory pin " "Info: + Longest memory to pin delay is 15.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0 1 MEM EC10_C 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC10_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~reg_ra0'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 4.400 ns altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~mem_cell_ra0 2 MEM EC10_C 1 " "Info: 2: + IC(0.000 ns) + CELL(4.400 ns) = 4.400 ns; Loc. = EC10_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[7\]~mem_cell_ra0'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "4.400 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 5.800 ns altsyncram:altsyncram_component\|altrom:rom\|q\[7\] 3 MEM EC10_C 1 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 5.800 ns; Loc. = EC10_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[7\]'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "1.400 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 altsyncram:altsyncram_component|altrom:rom|q[7] } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(6.300 ns) 15.800 ns q\[7\] 4 PIN PIN_17 0 " "Info: 4: + IC(3.700 ns) + CELL(6.300 ns) = 15.800 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "10.000 ns" { altsyncram:altsyncram_component|altrom:rom|q[7] q[7] } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.100 ns 76.58 % " "Info: Total cell delay = 12.100 ns ( 76.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns 23.42 % " "Info: Total interconnect delay = 3.700 ns ( 23.42 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "15.800 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 altsyncram:altsyncram_component|altrom:rom|q[7] q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.800 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 altsyncram:altsyncram_component|altrom:rom|q[7] q[7] } { 0.000ns 0.000ns 0.000ns 3.700ns } { 0.000ns 4.400ns 1.400ns 6.300ns } } }  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "15.800 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 altsyncram:altsyncram_component|altrom:rom|q[7] q[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.800 ns" { altsyncram:altsyncram_component|altrom:rom|q[7]~reg_ra0 altsyncram:altsyncram_component|altrom:rom|q[7]~mem_cell_ra0 altsyncram:altsyncram_component|altrom:rom|q[7] q[7] } { 0.000ns 0.000ns 0.000ns 3.700ns } { 0.000ns 4.400ns 1.400ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4 address\[4\] inclock -0.700 ns memory " "Info: th for memory \"altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4\" (data pin = \"address\[4\]\", clock pin = \"inclock\") is -0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.400 ns + Longest memory " "Info: + Longest clock path from clock \"inclock\" to destination memory is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_55 80 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 80; CLK Node = 'inclock'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { inclock } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 53 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4 2 MEM EC2_C 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = EC2_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "0.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.500 ns + " "Info: + Micro hold delay of destination is 0.500 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns address\[4\] 1 PIN PIN_125 8 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_125; Fanout = 8; PIN Node = 'address\[4\]'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "" { address[4] } "NODE_NAME" } "" } } { "SIN_ROM.VHD" "" { Text "E:/lhh/mokuai/rom/SIN_ROM.VHD" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.800 ns) 3.600 ns altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4 2 MEM EC2_C 1 " "Info: 2: + IC(0.800 ns) + CELL(0.800 ns) = 3.600 ns; Loc. = EC2_C; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altrom:rom\|q\[0\]~reg_ra4'" {  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "1.600 ns" { address[4] altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 77.78 % " "Info: Total cell delay = 2.800 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 22.22 % " "Info: Total interconnect delay = 0.800 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "3.600 ns" { address[4] altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { address[4] address[4]~out altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}  } { { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "2.400 ns" { inclock altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" "" { Report "E:/lhh/mokuai/rom/db/SIN_ROM_cmp.qrpt" Compiler "SIN_ROM" "UNKNOWN" "V1" "E:/lhh/mokuai/rom/db/SIN_ROM.quartus_db" { Floorplan "E:/lhh/mokuai/rom/" "" "3.600 ns" { address[4] altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.600 ns" { address[4] address[4]~out altsyncram:altsyncram_component|altrom:rom|q[0]~reg_ra4 } { 0.000ns 0.000ns 0.800ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 23 16:15:14 2005 " "Info: Processing ended: Sat Jul 23 16:15:14 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}