sin_rom.fit.talkback.xml

该源码为几个正弦ROM,已经编译并通过,可以直接下载,不需要,内部含有正弦ROM表,还有ROM的宏模块

		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[4]</name>
		<pin__>125</pin__>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[5]</name>
		<pin__>67</pin__>
		<col.>8</col.>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[6]</name>
		<pin__>69</pin__>
		<col.>6</col.>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[7]</name>
		<pin__>116</pin__>
		<col.>7</col.>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[8]</name>
		<pin__>63</pin__>
		<col.>11</col.>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>address[9]</name>
		<pin__>64</pin__>
		<col.>10</col.>
		<fan_out>8</fan_out>
		<global>no</global>
		<i_o_register>no</i_o_register>
		<use_local_routing_input>no</use_local_routing_input>
		<power_up_high>no</power_up_high>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_ce>no</single_pin_ce>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</input_pins>
<output_pins>
	<row>
		<name>q[0]</name>
		<pin__>14</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[1]</name>
		<pin__>101</pin__>
		<row>A</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[2]</name>
		<pin__>100</pin__>
		<row>A</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[3]</name>
		<pin__>8</pin__>
		<row>A</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[4]</name>
		<pin__>20</pin__>
		<row>D</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[5]</name>
		<pin__>12</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[6]</name>
		<pin__>96</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
	<row>
		<name>q[7]</name>
		<pin__>17</pin__>
		<row>C</row>
		<i_o_register>no</i_o_register>
		<use_local_routing_output>no</use_local_routing_output>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<single_pin_oe>no</single_pin_oe>
		<single_pin_ce>no</single_pin_ce>
		<open_drain>no</open_drain>
		<tri_primitive>no</tri_primitive>
		<i_o_standard>LVTTL/LVCMOS</i_o_standard>
	</row>
</output_pins>
<compilation_summary>
	<flow_status>Successful - Sat Jul 23 16:15:06 2005</flow_status>
	<quartus_ii_version>5.0 Build 148 04/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>SIN_ROM</revision_name>
	<top_level_entity_name>sin_rom</top_level_entity_name>
	<family>ACEX1K</family>
	<device>EP1K30TC144-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>0 / 1,728 ( 0 % )</total_logic_elements>
	<total_pins>19 / 102 ( 18 % )</total_pins>
	<total_memory_bits>8,192 / 24,576 ( 33 % )</total_memory_bits>
	<total_plls>0</total_plls>
</compilation_summary>
<compile_id>C8B60CEF</compile_id>
<files>
	<top>E:/lhh/mokuai/rom/SIN_ROM.VHD</top>
	<extensions>
		<ext ext_name="vhd">1</ext>
		<ext ext_name="tdf">2</ext>
		<ext ext_name="inc">11</ext>
		<ext ext_name="lst">1</ext>
		<ext ext_name="mif">1</ext>
	</extensions>
	<sub_files>
		<sub_file>E:/lhh/mokuai/rom/SIN_ROM.VHD</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_mux.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/lpm_decode.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/aglobal50.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altsyncram.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altrom.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altram.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altdpram.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altqpram.inc</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/cbx.lst</sub_file>
		<sub_file>d:/altera/quartus50/libraries/megafunctions/altrom.tdf</sub_file>
		<sub_file>d:/altera/quartus50/libraries/others/maxplus2/memmodes.inc</sub_file>
		<sub_file>E:/lhh/mokuai/rom/dds_sin.mif</sub_file>
	</sub_files>
</files>
<architecture>
	<family>ACEX1K</family>
	<auto_device>OFF</auto_device>
	<device>EP1K30TC144-3</device>
</architecture>
<pkg_io>
	<pin_std count="19">LVTTL/LVCMOS</pin_std>
</pkg_io>
</talkback>