hdpdeps.ref

基于fpga和xinlinx ise 的7段码led显示程序

V1 5
FL E:/CD_ROM/20万门Example/7SegClock_HLD3/7SegClockForHLD3(20040911)(END)/top.vhd 2004/09/11.18:39:40
EN work/CLOCK \
      FL E:/CD_ROM/20万门Example/7SegClock_HLD3/7SegClockForHLD3(20040911)(END)/top.vhd \
      PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED
AR work/CLOCK/BEHAVIORAL \
      FL E:/CD_ROM/20万门Example/7SegClock_HLD3/7SegClockForHLD3(20040911)(END)/top.vhd \
      EN work/CLOCK
FL E:/MyDocument(2004)/YYYY/YYYY/NewHLD4/lab/7SegClockForHLD3(20040911)(END)/top.vhd 2004/09/11.18:39:40
FL e:/mydocument(2004)/7segforhld3/top.vhd 2004/09/11.18:39:40