pulse.tan.rpt

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-

; N/A           ; None        ; -3.675 ns ; f[0] ; zz[4] ; clk      ;
; N/A           ; None        ; -3.684 ns ; f[1] ; zz[4] ; clk      ;
; N/A           ; None        ; -3.696 ns ; f[0] ; zz[5] ; clk      ;
; N/A           ; None        ; -3.705 ns ; f[1] ; zz[5] ; clk      ;
; N/A           ; None        ; -3.709 ns ; f[4] ; a     ; clk      ;
; N/A           ; None        ; -3.767 ns ; z[5] ; zz[5] ; clk      ;
; N/A           ; None        ; -3.768 ns ; z[0] ; zz[1] ; clk      ;
; N/A           ; None        ; -3.807 ns ; z[4] ; zz[4] ; clk      ;
; N/A           ; None        ; -3.879 ns ; f[0] ; zz[3] ; clk      ;
; N/A           ; None        ; -3.921 ns ; z[4] ; zz[5] ; clk      ;
; N/A           ; None        ; -4.042 ns ; z[3] ; a     ; clk      ;
; N/A           ; None        ; -4.106 ns ; z[0] ; a     ; clk      ;
; N/A           ; None        ; -4.128 ns ; f[0] ; b     ; clk      ;
; N/A           ; None        ; -4.260 ns ; z[4] ; a     ; clk      ;
; N/A           ; None        ; -4.291 ns ; z[5] ; a     ; clk      ;
; N/A           ; None        ; -4.340 ns ; z[1] ; zz[4] ; clk      ;
; N/A           ; None        ; -4.380 ns ; z[1] ; zz[5] ; clk      ;
; N/A           ; None        ; -4.414 ns ; f[2] ; b     ; clk      ;
; N/A           ; None        ; -4.451 ns ; z[0] ; zz[4] ; clk      ;
; N/A           ; None        ; -4.453 ns ; f[3] ; b     ; clk      ;
; N/A           ; None        ; -4.491 ns ; z[0] ; zz[5] ; clk      ;
; N/A           ; None        ; -4.515 ns ; z[2] ; zz[4] ; clk      ;
; N/A           ; None        ; -4.555 ns ; z[2] ; zz[5] ; clk      ;
; N/A           ; None        ; -4.586 ns ; z[3] ; b     ; clk      ;
; N/A           ; None        ; -4.648 ns ; f[5] ; b     ; clk      ;
; N/A           ; None        ; -4.650 ns ; z[0] ; b     ; clk      ;
; N/A           ; None        ; -4.669 ns ; f[1] ; b     ; clk      ;
; N/A           ; None        ; -4.750 ns ; f[4] ; b     ; clk      ;
; N/A           ; None        ; -4.793 ns ; z[1] ; a     ; clk      ;
; N/A           ; None        ; -4.804 ns ; z[4] ; b     ; clk      ;
; N/A           ; None        ; -4.828 ns ; z[2] ; a     ; clk      ;
; N/A           ; None        ; -4.835 ns ; z[5] ; b     ; clk      ;
; N/A           ; None        ; -5.337 ns ; z[1] ; b     ; clk      ;
; N/A           ; None        ; -5.372 ns ; z[2] ; b     ; clk      ;
+---------------+-------------+-----------+------+-------+----------+


+------------------------------------------------------------------------------+
; Minimum tco                                                                  ;
+---------------+------------------+----------------+--------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From   ; To ; From Clock ;
+---------------+------------------+----------------+--------+----+------------+
; N/A           ; None             ; 6.801 ns       ; q~reg0 ; q  ; clk        ;
+---------------+------------------+----------------+--------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Jul 20 17:12:16 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off pulse -c pulse --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 419.99 MHz between source register zz[2] and destination register a (period= 2.381 ns)
    Info: + Longest register to register delay is 2.215 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz[2]'
        Info: 2: + IC(0.546 ns) + CELL(0.280 ns) = 0.826 ns; Loc. = LC_X30_Y28_N6; Fanout = 2; COMB Node = 'add~47'
        Info: 3: + IC(0.315 ns) + CELL(0.075 ns) = 1.216 ns; Loc. = LC_X30_Y28_N8; Fanout = 2; COMB Node = 'add~61'
        Info: 4: + IC(0.348 ns) + CELL(0.075 ns) = 1.639 ns; Loc. = LC_X30_Y28_N0; Fanout = 2; COMB Node = 'reduce_nor~2'
        Info: 5: + IC(0.491 ns) + CELL(0.085 ns) = 2.215 ns; Loc. = LC_X30_Y28_N5; Fanout = 10; REG Node = 'a'
        Info: Total cell delay = 0.515 ns ( 23.25 % )
        Info: Total interconnect delay = 1.700 ns ( 76.75 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 2.787 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X30_Y28_N5; Fanout = 10; REG Node = 'a'
            Info: Total cell delay = 1.267 ns ( 45.46 % )
            Info: Total interconnect delay = 1.520 ns ( 54.54 % )
        Info: - Longest clock path from clock clk to source register is 2.787 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
            Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz[2]'
            Info: Total cell delay = 1.267 ns ( 45.46 % )
            Info: Total interconnect delay = 1.520 ns ( 54.54 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register b (data pin = z[3], clock pin = clk) is 5.986 ns
    Info: + Longest pin to register delay is 8.763 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'z[3]'
        Info: 2: + IC(4.065 ns) + CELL(0.366 ns) = 5.518 ns; Loc. = LC_X29_Y28_N3; Fanout = 1; COMB Node = 'reduce_nor~97'
        Info: 3: + IC(0.890 ns) + CELL(0.280 ns) = 6.688 ns; Loc. = LC_X30_Y29_N6; Fanout = 2; COMB Node = 'reduce_nor~0'
        Info: 4: + IC(0.975 ns) + CELL(0.280 ns) = 7.943 ns; Loc. = LC_X31_Y28_N7; Fanout = 1; COMB Node = 'b~177'
        Info: 5: + IC(0.501 ns) + CELL(0.319 ns) = 8.763 ns; Loc. = LC_X30_Y28_N1; Fanout = 10; REG Node = 'b'
        Info: Total cell delay = 2.332 ns ( 26.61 % )
        Info: Total interconnect delay = 6.431 ns ( 73.39 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock clk to destination register is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X30_Y28_N1; Fanout = 10; REG Node = 'b'
        Info: Total cell delay = 1.267 ns ( 45.46 % )
        Info: Total interconnect delay = 1.520 ns ( 54.54 % )
Info: tco from clock clk to destination pin q through register q~reg0 is 6.801 ns
    Info: + Longest clock path from clock clk to source register is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'
        Info: Total cell delay = 1.267 ns ( 45.46 % )
        Info: Total interconnect delay = 1.520 ns ( 54.54 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'
        Info: 2: + IC(1.454 ns) + CELL(2.404 ns) = 3.858 ns; Loc. = PIN_L7; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.404 ns ( 62.31 % )
        Info: Total interconnect delay = 1.454 ns ( 37.69 % )
Info: th for register zz[2] (data pin = z[2], clock pin = clk) is -2.660 ns
    Info: + Longest clock path from clock clk to destination register is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz[2]'
        Info: Total cell delay = 1.267 ns ( 45.46 % )
        Info: Total interconnect delay = 1.520 ns ( 54.54 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.547 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_G9; Fanout = 4; PIN Node = 'z[2]'
        Info: 2: + IC(3.836 ns) + CELL(0.075 ns) = 4.998 ns; Loc. = LC_X31_Y28_N4; Fanout = 1; COMB Node = 'add~16'
        Info: 3: + IC(0.326 ns) + CELL(0.223 ns) = 5.547 ns; Loc. = LC_X31_Y28_N2; Fanout = 4; REG Node = 'zz[2]'
        Info: Total cell delay = 1.385 ns ( 24.97 % )
        Info: Total interconnect delay = 4.162 ns ( 75.03 % )
Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.801 ns
    Info: + Shortest clock path from clock clk to source register is 2.787 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(1.520 ns) + CELL(0.542 ns) = 2.787 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'
        Info: Total cell delay = 1.267 ns ( 45.46 % )
        Info: Total interconnect delay = 1.520 ns ( 54.54 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 3.858 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y28_N9; Fanout = 1; REG Node = 'q~reg0'
        Info: 2: + IC(1.454 ns) + CELL(2.404 ns) = 3.858 ns; Loc. = PIN_L7; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.404 ns ( 62.31 % )
        Info: Total interconnect delay = 1.454 ns ( 37.69 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 20 17:12:17 2005
    Info: Elapsed time: 00:00:00