time.tan.rpt

用vhdl实现24小时计数器

; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[1] ; cnt1[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[0] ; cnt1[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[0] ; cnt0[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[2] ; cnt1[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[3] ; cnt1[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[0] ; cnt1[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[2] ; cnt1[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[2] ; cnt1[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[2] ; cnt0[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[3] ; cnt0[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[3] ; cnt0[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[2] ; cnt0[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[2] ; cnt0[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[0] ; cnt0[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[0] ; cnt0[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[0] ; cnt0[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[3] ; cnt1[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[3] ; cnt0[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[1] ; cnt0[0] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[1] ; cnt0[3] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt0[1] ; cnt0[1] ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt1[3] ; cnt0[2] ; clk        ; clk      ; None                        ; None                      ; None                    ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+---------+-------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To    ; From Clock ;
+-------+--------------+------------+---------+-------+------------+
; N/A   ; None         ; 6.601 ns   ; cnt1[1] ; h1[1] ; clk        ;
; N/A   ; None         ; 6.598 ns   ; cnt0[0] ; h0[0] ; clk        ;
; N/A   ; None         ; 6.597 ns   ; cnt1[3] ; h1[3] ; clk        ;
; N/A   ; None         ; 6.595 ns   ; cnt0[2] ; h0[2] ; clk        ;
; N/A   ; None         ; 6.592 ns   ; cnt0[3] ; h0[3] ; clk        ;
; N/A   ; None         ; 6.590 ns   ; cnt1[0] ; h1[0] ; clk        ;
; N/A   ; None         ; 6.585 ns   ; cnt1[2] ; h1[2] ; clk        ;
; N/A   ; None         ; 6.552 ns   ; cnt0[1] ; h0[1] ; clk        ;
+-------+--------------+------------+---------+-------+------------+


+----------------------------------------------------------------------------------+
; Minimum tco                                                                      ;
+---------------+------------------+----------------+---------+-------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From    ; To    ; From Clock ;
+---------------+------------------+----------------+---------+-------+------------+
; N/A           ; None             ; 6.552 ns       ; cnt0[1] ; h0[1] ; clk        ;
; N/A           ; None             ; 6.585 ns       ; cnt1[2] ; h1[2] ; clk        ;
; N/A           ; None             ; 6.590 ns       ; cnt1[0] ; h1[0] ; clk        ;
; N/A           ; None             ; 6.592 ns       ; cnt0[3] ; h0[3] ; clk        ;
; N/A           ; None             ; 6.595 ns       ; cnt0[2] ; h0[2] ; clk        ;
; N/A           ; None             ; 6.597 ns       ; cnt1[3] ; h1[3] ; clk        ;
; N/A           ; None             ; 6.598 ns       ; cnt0[0] ; h0[0] ; clk        ;
; N/A           ; None             ; 6.601 ns       ; cnt1[1] ; h1[1] ; clk        ;
+---------------+------------------+----------------+---------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun Mar 13 23:19:05 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off time -c time --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 366.97 MHz between source register cnt0[3] and destination register cnt1[1] (period= 2.725 ns)
    Info: + Longest register to register delay is 2.559 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y29_N3; Fanout = 6; REG Node = 'cnt0[3]'
        Info: 2: + IC(0.826 ns) + CELL(0.075 ns) = 0.901 ns; Loc. = LC_X9_Y29_N4; Fanout = 1; COMB Node = 'process0~35'
        Info: 3: + IC(0.754 ns) + CELL(0.366 ns) = 2.021 ns; Loc. = LC_X9_Y29_N6; Fanout = 2; COMB Node = 'process0~0'
        Info: 4: + IC(0.315 ns) + CELL(0.223 ns) = 2.559 ns; Loc. = LC_X9_Y29_N8; Fanout = 5; REG Node = 'cnt1[1]'
        Info: Total cell delay = 0.664 ns ( 25.95 % )
        Info: Total interconnect delay = 1.895 ns ( 74.05 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 2.833 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.833 ns; Loc. = LC_X9_Y29_N8; Fanout = 5; REG Node = 'cnt1[1]'
            Info: Total cell delay = 1.267 ns ( 44.72 % )
            Info: Total interconnect delay = 1.566 ns ( 55.28 % )
        Info: - Longest clock path from clock clk to source register is 2.833 ns
            Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
            Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.833 ns; Loc. = LC_X8_Y29_N3; Fanout = 6; REG Node = 'cnt0[3]'
            Info: Total cell delay = 1.267 ns ( 44.72 % )
            Info: Total interconnect delay = 1.566 ns ( 55.28 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock clk to destination pin h1[1] through register cnt1[1] is 6.601 ns
    Info: + Longest clock path from clock clk to source register is 2.833 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.833 ns; Loc. = LC_X9_Y29_N8; Fanout = 5; REG Node = 'cnt1[1]'
        Info: Total cell delay = 1.267 ns ( 44.72 % )
        Info: Total interconnect delay = 1.566 ns ( 55.28 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.612 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y29_N8; Fanout = 5; REG Node = 'cnt1[1]'
        Info: 2: + IC(1.208 ns) + CELL(2.404 ns) = 3.612 ns; Loc. = PIN_G16; Fanout = 0; PIN Node = 'h1[1]'
        Info: Total cell delay = 2.404 ns ( 66.56 % )
        Info: Total interconnect delay = 1.208 ns ( 33.44 % )
Info: Minimum tco from clock clk to destination pin h0[1] through register cnt0[1] is 6.552 ns
    Info: + Shortest clock path from clock clk to source register is 2.833 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(1.566 ns) + CELL(0.542 ns) = 2.833 ns; Loc. = LC_X8_Y29_N9; Fanout = 6; REG Node = 'cnt0[1]'
        Info: Total cell delay = 1.267 ns ( 44.72 % )
        Info: Total interconnect delay = 1.566 ns ( 55.28 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 3.563 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y29_N9; Fanout = 6; REG Node = 'cnt0[1]'
        Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_C17; Fanout = 0; PIN Node = 'h0[1]'
        Info: Total cell delay = 2.404 ns ( 67.47 % )
        Info: Total interconnect delay = 1.159 ns ( 32.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 13 23:19:05 2005
    Info: Elapsed time: 00:00:00