shifter.tan.qmsg

用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II

{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[2\] dout\[2\]~reg0 6.666 ns register " "Info: tco from clock clk to destination pin dout\[2\] through register dout\[2\]~reg0 is 6.666 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.926 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 2.926 ns dout\[2\]~reg0 2 REG LC_X1_Y1_N5 1 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.201 ns" { clk dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 43.30 % " "Info: Total cell delay = 1.267 ns ( 43.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns 56.70 % " "Info: Total interconnect delay = 1.659 ns ( 56.70 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.584 ns + Longest register pin " "Info: + Longest register to pin delay is 3.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[2\]~reg0 1 REG LC_X1_Y1_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(2.376 ns) 3.584 ns dout\[2\] 2 PIN PIN_W21 0 " "Info: 2: + IC(1.208 ns) + CELL(2.376 ns) = 3.584 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'dout\[2\]'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.584 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns 66.29 % " "Info: Total cell delay = 2.376 ns ( 66.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.208 ns 33.71 % " "Info: Total interconnect delay = 1.208 ns ( 33.71 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.584 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } }  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.584 ns" { dout[2]~reg0 dout[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "dout\[2\]~reg0 left_right clk -1.645 ns register " "Info: th for register dout\[2\]~reg0 (data pin = left_right, clock pin = clk) is -1.645 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.926 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 2.926 ns dout\[2\]~reg0 2 REG LC_X1_Y1_N5 1 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.201 ns" { clk dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 43.30 % " "Info: Total cell delay = 1.267 ns ( 43.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns 56.70 % " "Info: Total interconnect delay = 1.659 ns ( 56.70 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.671 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns left_right 1 PIN PIN_U19 4 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U19; Fanout = 4; PIN Node = 'left_right'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { left_right } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.214 ns) + CELL(0.223 ns) 4.671 ns dout\[2\]~reg0 2 REG LC_X1_Y1_N5 1 " "Info: 2: + IC(3.214 ns) + CELL(0.223 ns) = 4.671 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout\[2\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.437 ns" { left_right dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 31.19 % " "Info: Total cell delay = 1.457 ns ( 31.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.214 ns 68.81 % " "Info: Total interconnect delay = 3.214 ns ( 68.81 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "4.671 ns" { left_right dout[2]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[2]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "4.671 ns" { left_right dout[2]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dout\[0\] dout\[0\]~reg0 6.253 ns register " "Info: Minimum tco from clock clk to destination pin dout\[0\] through register dout\[0\]~reg0 is 6.253 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.926 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.926 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 2.926 ns dout\[0\]~reg0 2 REG LC_X1_Y1_N6 1 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; REG Node = 'dout\[0\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.201 ns" { clk dout[0]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns 43.30 % " "Info: Total cell delay = 1.267 ns ( 43.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns 56.70 % " "Info: Total interconnect delay = 1.659 ns ( 56.70 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[0]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.171 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[0\]~reg0 1 REG LC_X1_Y1_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; REG Node = 'dout\[0\]~reg0'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "" { dout[0]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(2.376 ns) 3.171 ns dout\[0\] 2 PIN PIN_U20 0 " "Info: 2: + IC(0.795 ns) + CELL(2.376 ns) = 3.171 ns; Loc. = PIN_U20; Fanout = 0; PIN Node = 'dout\[0\]'" {  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.171 ns" { dout[0]~reg0 dout[0] } "NODE_NAME" } } } { "d:/md/vhd/shifter/shifter.vhd" "" "" { Text "d:/md/vhd/shifter/shifter.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns 74.93 % " "Info: Total cell delay = 2.376 ns ( 74.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.795 ns 25.07 % " "Info: Total interconnect delay = 0.795 ns ( 25.07 % )" {  } {  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.171 ns" { dout[0]~reg0 dout[0] } "NODE_NAME" } } }  } 0}  } { { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "2.926 ns" { clk dout[0]~reg0 } "NODE_NAME" } } } { "d:/md/vhd/shifter/db/shifter_cmp.qrpt" "" "" { Report "d:/md/vhd/shifter/db/shifter_cmp.qrpt" Compiler "shifter" "UNKNOWN" "V1" "d:/md/vhd/shifter/db/shifter.quartus_db" { Floorplan "" "" "3.171 ns" { dout[0]~reg0 dout[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jul 02 09:46:07 2005 " "Info: Processing ended: Sat Jul 02 09:46:07 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}