shifter.tan.rpt

用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II

+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 6.666 ns   ; dout[2]~reg0 ; dout[2] ; clk        ;
; N/A   ; None         ; 6.645 ns   ; dout[1]~reg0 ; dout[1] ; clk        ;
; N/A   ; None         ; 6.645 ns   ; dout[3]~reg0 ; dout[3] ; clk        ;
; N/A   ; None         ; 6.253 ns   ; dout[0]~reg0 ; dout[0] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+------------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To           ; To Clock ;
+---------------+-------------+-----------+------------+--------------+----------+
; N/A           ; None        ; -1.645 ns ; left_right ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -1.645 ns ; left_right ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.869 ns ; left_right ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -1.871 ns ; left_right ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -1.882 ns ; din[1]     ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.923 ns ; din[2]     ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.001 ns ; load       ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.001 ns ; load       ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.115 ns ; din[1]     ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.156 ns ; din[2]     ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.237 ns ; din[1]     ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.241 ns ; din[2]     ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.301 ns ; din[3]     ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.305 ns ; din[3]     ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.369 ns ; din[0]     ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.371 ns ; din[0]     ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.628 ns ; load       ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.628 ns ; load       ; dout[1]~reg0 ; clk      ;
+---------------+-------------+-----------+------------+--------------+----------+


+-----------------------------------------------------------------------------------------+
; Minimum tco                                                                             ;
+---------------+------------------+----------------+--------------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From         ; To      ; From Clock ;
+---------------+------------------+----------------+--------------+---------+------------+
; N/A           ; None             ; 6.253 ns       ; dout[0]~reg0 ; dout[0] ; clk        ;
; N/A           ; None             ; 6.645 ns       ; dout[3]~reg0 ; dout[3] ; clk        ;
; N/A           ; None             ; 6.645 ns       ; dout[1]~reg0 ; dout[1] ; clk        ;
; N/A           ; None             ; 6.666 ns       ; dout[2]~reg0 ; dout[2] ; clk        ;
+---------------+------------------+----------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Jul 02 09:46:06 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shifter -c shifter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: No valid register-to-register paths exist for clock clk
Info: tsu for register dout[2]~reg0 (data pin = load, clock pin = clk) is 2.738 ns
    Info: + Longest pin to register delay is 5.654 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y21; Fanout = 4; PIN Node = 'load'
        Info: 2: + IC(3.697 ns) + CELL(0.870 ns) = 5.654 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.957 ns ( 34.61 % )
        Info: Total interconnect delay = 3.697 ns ( 65.39 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock clk to destination register is 2.926 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.267 ns ( 43.30 % )
        Info: Total interconnect delay = 1.659 ns ( 56.70 % )
Info: tco from clock clk to destination pin dout[2] through register dout[2]~reg0 is 6.666 ns
    Info: + Longest clock path from clock clk to source register is 2.926 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.267 ns ( 43.30 % )
        Info: Total interconnect delay = 1.659 ns ( 56.70 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.584 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: 2: + IC(1.208 ns) + CELL(2.376 ns) = 3.584 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'dout[2]'
        Info: Total cell delay = 2.376 ns ( 66.29 % )
        Info: Total interconnect delay = 1.208 ns ( 33.71 % )
Info: th for register dout[2]~reg0 (data pin = left_right, clock pin = clk) is -1.645 ns
    Info: + Longest clock path from clock clk to destination register is 2.926 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.267 ns ( 43.30 % )
        Info: Total interconnect delay = 1.659 ns ( 56.70 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.671 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_U19; Fanout = 4; PIN Node = 'left_right'
        Info: 2: + IC(3.214 ns) + CELL(0.223 ns) = 4.671 ns; Loc. = LC_X1_Y1_N5; Fanout = 1; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.457 ns ( 31.19 % )
        Info: Total interconnect delay = 3.214 ns ( 68.81 % )
Info: Minimum tco from clock clk to destination pin dout[0] through register dout[0]~reg0 is 6.253 ns
    Info: + Shortest clock path from clock clk to source register is 2.926 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 2.926 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; REG Node = 'dout[0]~reg0'
        Info: Total cell delay = 1.267 ns ( 43.30 % )
        Info: Total interconnect delay = 1.659 ns ( 56.70 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 3.171 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y1_N6; Fanout = 1; REG Node = 'dout[0]~reg0'
        Info: 2: + IC(0.795 ns) + CELL(2.376 ns) = 3.171 ns; Loc. = PIN_U20; Fanout = 0; PIN Node = 'dout[0]'
        Info: Total cell delay = 2.376 ns ( 74.93 % )
        Info: Total interconnect delay = 0.795 ns ( 25.07 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Jul 02 09:46:07 2005
    Info: Elapsed time: 00:00:00