config_controller.tan.summary

来自「用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源」· SUMMARY 代码 · 共 87 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.900 ns
From           : status_n
To             : u10
From Clock     : 
To Clock       : cpld_clkosc
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.600 ns
From           : u11
To             : flash_cs_n
From Clock     : cpld_clkosc
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.500 ns
From           : D[0]
To             : pld_data0
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.400 ns
From           : config_done
To             : u11
From Clock     : 
To Clock       : cpld_clkosc
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.000 ns
From           : u5
To             : flash_reset_n
From Clock     : cpld_clkosc
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 7.500 ns
From           : D[0]
To             : pld_data0
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'cpld_clkosc'
Slack          : N/A
Required Time  : None
Actual Time    : 125.00 MHz ( period = 8.000 ns )
From           : u12
To             : u7
From Clock     : cpld_clkosc
To Clock       : cpld_clkosc
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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