config_controller.map.qmsg

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jun 19 10:39:44 2005 " "Info: Processing started: Sun Jun 19 10:39:44 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off config_controller -c config_controller " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off config_controller -c config_controller" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_bit_counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_bit_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_bit_counter-SYN " "Info: Found design unit 1: data_bit_counter-SYN" {  } { { "D:/config_controller/data_bit_counter.vhd" "data_bit_counter-SYN" "" { Text "D:/config_controller/data_bit_counter.vhd" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 data_bit_counter " "Info: Found entity 1: data_bit_counter" {  } { { "D:/config_controller/data_bit_counter.vhd" "data_bit_counter" "" { Text "D:/config_controller/data_bit_counter.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dclk_divider.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dclk_divider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dclk_divider-SYN " "Info: Found design unit 1: dclk_divider-SYN" {  } { { "D:/config_controller/dclk_divider.vhd" "dclk_divider-SYN" "" { Text "D:/config_controller/dclk_divider.vhd" 56 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 dclk_divider " "Info: Found entity 1: dclk_divider" {  } { { "D:/config_controller/dclk_divider.vhd" "dclk_divider" "" { Text "D:/config_controller/dclk_divider.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shift_register.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shift_register.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shift_register-SYN " "Info: Found design unit 1: shift_register-SYN" {  } { { "D:/config_controller/shift_register.vhd" "shift_register-SYN" "" { Text "D:/config_controller/shift_register.vhd" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shift_register " "Info: Found entity 1: shift_register" {  } { { "D:/config_controller/shift_register.vhd" "shift_register" "" { Text "D:/config_controller/shift_register.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "address_counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file address_counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 address_counter-SYN " "Info: Found design unit 1: address_counter-SYN" {  } { { "D:/config_controller/address_counter.vhd" "address_counter-SYN" "" { Text "D:/config_controller/address_counter.vhd" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 address_counter " "Info: Found entity 1: address_counter" {  } { { "D:/config_controller/address_counter.vhd" "address_counter" "" { Text "D:/config_controller/address_counter.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "config_controller.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file config_controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 config_controller-config " "Info: Found design unit 1: config_controller-config" {  } { { "D:/config_controller/config_controller.vhd" "config_controller-config" "" { Text "D:/config_controller/config_controller.vhd" 67 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 config_controller " "Info: Found entity 1: config_controller" {  } { { "D:/config_controller/config_controller.vhd" "config_controller" "" { Text "D:/config_controller/config_controller.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "lpm_shiftreg" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 43 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 194 -1 0 } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 195 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "pld_msel1 GND " "Warning: Pin pld_msel1 stuck at GND" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 47 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "cpld_clkosc " "Info: Promoted clock signal driven by pin cpld_clkosc to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "103 " "Info: Implemented 103 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "35 " "Info: Implemented 35 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "55 " "Info: Implemented 55 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 19 10:40:16 2005 " "Info: Processing ended: Sun Jun 19 10:40:16 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Info: Elapsed time: 00:00:31" {  } {  } 0}  } {  } 0}