config_controller.tan.qmsg

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

{ "Info" "ITDB_TH_RESULT" "u11 config_done cpld_clkosc -0.400 ns register " "Info: th for register u11 (data pin = config_done, clock pin = cpld_clkosc) is -0.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc destination 2.600 ns + Longest register " "Info: + Longest clock path from clock cpld_clkosc to destination register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns u11 2 REG LC111 3 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC111; Fanout = 3; REG Node = 'u11'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc u11 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 200 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u11 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 200 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns config_done 1 PIN PIN_85 2 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_85; Fanout = 2; PIN Node = 'config_done'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { config_done } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.000 ns) 4.000 ns u11 2 REG LC111 3 " "Info: 2: + IC(2.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC111; Fanout = 3; REG Node = 'u11'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "3.000 ns" { config_done u11 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 200 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 50.00 % " "Info: Total cell delay = 2.000 ns ( 50.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 50.00 % " "Info: Total interconnect delay = 2.000 ns ( 50.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.000 ns" { config_done u11 } "NODE_NAME" } } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u11 } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.000 ns" { config_done u11 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "cpld_clkosc flash_reset_n u5 5.000 ns register " "Info: Minimum tco from clock cpld_clkosc to destination pin flash_reset_n through register u5 is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc source 2.600 ns + Shortest register " "Info: + Shortest clock path from clock cpld_clkosc to source register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns u5 2 REG LC94 7 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC94; Fanout = 7; REG Node = 'u5'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc u5 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 194 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 194 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.200 ns + Shortest register pin " "Info: + Shortest register to pin delay is 1.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns u5 1 REG LC94 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC94; Fanout = 7; REG Node = 'u5'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { u5 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 194 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns flash_reset_n 2 PIN PIN_61 0 " "Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_61; Fanout = 0; PIN Node = 'flash_reset_n'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { u5 flash_reset_n } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns 100.00 % " "Info: Total cell delay = 1.200 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { u5 flash_reset_n } "NODE_NAME" } } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u5 } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { u5 flash_reset_n } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "D\[0\] pld_data0 7.500 ns Shortest " "Info: Shortest tpd from source pin D\[0\] to destination pin pld_data0 is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns D\[0\] 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'D\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { D[0] } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(3.300 ns) 6.300 ns data0~50 2 COMB LC97 1 " "Info: 2: + IC(2.000 ns) + CELL(3.300 ns) = 6.300 ns; Loc. = LC97; Fanout = 1; COMB Node = 'data0~50'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.300 ns" { D[0] data0~50 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 154 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.500 ns pld_data0 3 PIN PIN_63 0 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.500 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'pld_data0'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { data0~50 pld_data0 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 73.33 % " "Info: Total cell delay = 5.500 ns ( 73.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 26.67 % " "Info: Total interconnect delay = 2.000 ns ( 26.67 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "7.500 ns" { D[0] data0~50 pld_data0 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 19 10:40:44 2005 " "Info: Processing ended: Sun Jun 19 10:40:44 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}