config_controller.tan.qmsg

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cpld_clkosc " "Info: Assuming node cpld_clkosc is an undefined clock" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } } { "e:/quartus4.1/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus4.1/bin/Assignment Editor.qase" 1 { { 0 "cpld_clkosc" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cpld_clkosc register data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\] register shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 125.0 MHz 8.0 ns Internal " "Info: Clock cpld_clkosc has Internal fmax of 125.0 MHz between source register data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\] and destination register shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] (period= 8.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\] 1 REG LC34 36 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC34; Fanout = 36; REG Node = 'data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.400 ns) 4.700 ns shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC4 3 " "Info: 2: + IC(2.300 ns) + CELL(2.400 ns) = 4.700 ns; Loc. = LC4; Fanout = 3; REG Node = 'shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.700 ns" { data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns 51.06 % " "Info: Total cell delay = 2.400 ns ( 51.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 48.94 % " "Info: Total interconnect delay = 2.300 ns ( 48.94 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.700 ns" { data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc destination 2.600 ns + Shortest register " "Info: + Shortest clock path from clock cpld_clkosc to destination register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC4; Fanout = 3; REG Node = 'shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc source 2.600 ns - Longest register " "Info: - Longest clock path from clock cpld_clkosc to source register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\] 2 REG LC34 36 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC34; Fanout = 36; REG Node = 'data_bit_counter:u3\|lpm_counter:lpm_counter_component\|dffs\[2\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] } "NODE_NAME" } } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.700 ns" { data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] D\[1\] cpld_clkosc 4.900 ns register " "Info: tsu for register shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] (data pin = D\[1\], clock pin = cpld_clkosc) is 4.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns + Longest pin register " "Info: + Longest pin to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns D\[1\] 1 PIN PIN_72 2 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_72; Fanout = 2; PIN Node = 'D\[1\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { D[1] } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.400 ns) 5.400 ns shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC4 3 " "Info: 2: + IC(2.000 ns) + CELL(2.400 ns) = 5.400 ns; Loc. = LC4; Fanout = 3; REG Node = 'shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "4.400 ns" { D[1] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 62.96 % " "Info: Total cell delay = 3.400 ns ( 62.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 37.04 % " "Info: Total interconnect delay = 2.000 ns ( 37.04 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.400 ns" { D[1] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.100 ns + " "Info: + Micro setup delay of destination is 2.100 ns" {  } { { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc destination 2.600 ns - Shortest register " "Info: - Shortest clock path from clock cpld_clkosc to destination register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\] 2 REG LC4 3 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC4; Fanout = 3; REG Node = 'shift_register:u4\|lpm_shiftreg:lpm_shiftreg_component\|dffs\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" "" "" { Text "e:/quartus4.1/libraries/megafunctions/lpm_shiftreg.tdf" 60 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.400 ns" { D[1] shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cpld_clkosc flash_oe_n u8 15.600 ns register " "Info: tco from clock cpld_clkosc to destination pin flash_oe_n through register u8 is 15.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cpld_clkosc source 2.600 ns + Longest register " "Info: + Longest clock path from clock cpld_clkosc to source register is 2.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns cpld_clkosc 1 CLK PIN_87 43 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_87; Fanout = 43; CLK Node = 'cpld_clkosc'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { cpld_clkosc } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.700 ns) 2.600 ns u8 2 REG LC107 8 " "Info: 2: + IC(0.000 ns) + CELL(0.700 ns) = 2.600 ns; Loc. = LC107; Fanout = 8; REG Node = 'u8'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "0.700 ns" { cpld_clkosc u8 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 197 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 100.00 % " "Info: Total cell delay = 2.600 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u8 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.200 ns + " "Info: + Micro clock to output delay of source is 1.200 ns" {  } { { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 197 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register pin " "Info: + Longest register to pin delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns u8 1 REG LC107 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC107; Fanout = 8; REG Node = 'u8'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { u8 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 197 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(3.300 ns) 5.300 ns loading_led~11 2 COMB LC99 29 " "Info: 2: + IC(2.000 ns) + CELL(3.300 ns) = 5.300 ns; Loc. = LC99; Fanout = 29; COMB Node = 'loading_led~11'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.300 ns" { u8 loading_led~11 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(3.300 ns) 10.600 ns loading_led~14 3 COMB LC59 1 " "Info: 3: + IC(2.000 ns) + CELL(3.300 ns) = 10.600 ns; Loc. = LC59; Fanout = 1; COMB Node = 'loading_led~14'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.300 ns" { loading_led~11 loading_led~14 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 11.800 ns flash_oe_n 4 PIN PIN_30 0 " "Info: 4: + IC(0.000 ns) + CELL(1.200 ns) = 11.800 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'flash_oe_n'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { loading_led~14 flash_oe_n } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.800 ns 66.10 % " "Info: Total cell delay = 7.800 ns ( 66.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 33.90 % " "Info: Total interconnect delay = 4.000 ns ( 33.90 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "11.800 ns" { u8 loading_led~11 loading_led~14 flash_oe_n } "NODE_NAME" } } }  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "2.600 ns" { cpld_clkosc u8 } "NODE_NAME" } } } { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "11.800 ns" { u8 loading_led~11 loading_led~14 flash_oe_n } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "D\[0\] pld_data0 7.500 ns Longest " "Info: Longest tpd from source pin D\[0\] to destination pin pld_data0 is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns D\[0\] 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'D\[0\]'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "" { D[0] } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(3.300 ns) 6.300 ns data0~50 2 COMB LC97 1 " "Info: 2: + IC(2.000 ns) + CELL(3.300 ns) = 6.300 ns; Loc. = LC97; Fanout = 1; COMB Node = 'data0~50'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "5.300 ns" { D[0] data0~50 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 154 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 7.500 ns pld_data0 3 PIN PIN_63 0 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.500 ns; Loc. = PIN_63; Fanout = 0; PIN Node = 'pld_data0'" {  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "1.200 ns" { data0~50 pld_data0 } "NODE_NAME" } } } { "D:/config_controller/config_controller.vhd" "" "" { Text "D:/config_controller/config_controller.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns 73.33 % " "Info: Total cell delay = 5.500 ns ( 73.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 26.67 % " "Info: Total interconnect delay = 2.000 ns ( 26.67 % )" {  } {  } 0}  } { { "D:/config_controller/db/config_controller_cmp.qrpt" "" "" { Report "D:/config_controller/db/config_controller_cmp.qrpt" Compiler "config_controller" "UNKNOWN" "V1" "D:/config_controller/db/config_controller.quartus_db" { Floorplan "" "" "7.500 ns" { D[0] data0~50 pld_data0 } "NODE_NAME" } } }  } 0}