config_controller.tan.rpt

用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。

; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                          ;
+------------------------------+-------+---------------+----------------------------------+-------------+---------------+-------------+-------------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From        ; To            ; From Clock  ; To Clock    ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------+---------------+-------------+-------------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.900 ns                         ; status_n    ; u10           ;             ; cpld_clkosc ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 15.600 ns                        ; u11         ; flash_cs_n    ; cpld_clkosc ;             ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 7.500 ns                         ; D[0]        ; pld_data0     ;             ;             ; 0            ;
; Worst-case th                ; N/A   ; None          ; -0.400 ns                        ; config_done ; u11           ;             ; cpld_clkosc ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 5.000 ns                         ; u5          ; flash_reset_n ; cpld_clkosc ;             ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 7.500 ns                         ; D[0]        ; pld_data0     ;             ;             ; 0            ;
; Clock Setup: 'cpld_clkosc'   ; N/A   ; None          ; 125.00 MHz ( period = 8.000 ns ) ; u12         ; u7            ; cpld_clkosc ; cpld_clkosc ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;             ;               ;             ;             ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------+---------------+-------------+-------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; cpld_clkosc     ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'cpld_clkosc'                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                          ; To                                                            ; From Clock  ; To Clock    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------+---------------------------------------------------------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[1] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[0] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[2] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[1] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;
; N/A                                     ; 125.00 MHz ( period = 8.000 ns )                    ; data_bit_counter:u3|lpm_counter:lpm_counter_component|dffs[0] ; shift_register:u4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; cpld_clkosc ; cpld_clkosc ; None                        ; None                      ; None                    ;