📄 config_controller.vwf

📁 用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。
💻 VWF
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	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[7]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[6]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[5]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[4]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[3]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[2]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[1]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("a[0]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("config_n")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("DCLK")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("error_led")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_a20")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_a21")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_a22")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_cs_n")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_oe_n")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_reset_n")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("flash_rw_n")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("loading_led")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("pld_data0")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("pld_msel0")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("pld_msel1")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

TRANSITION_LIST("user_led")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 10;
			LEVEL X FOR 100000.0;
		}
	}
}

DISPLAY_LINE
{
	CHANNEL = "status_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "reset_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "config_done";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "D";
	EXPAND_STATUS = EXPANDED;
	RADIX = Hexadecimal;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
	CHILDREN = 4, 5, 6, 7, 8, 9, 10, 11;
}

DISPLAY_LINE
{
	CHANNEL = "D[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "D[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Unsigned;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 3;
}

DISPLAY_LINE
{
	CHANNEL = "cpld_clkosc";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "DCLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "pld_data0";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 0;
	CHILDREN = 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35;
}

DISPLAY_LINE
{
	CHANNEL = "a[19]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[18]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[17]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[16]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "a[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 35;
	TREE_LEVEL = 1;
	PARENT = 15;
}

DISPLAY_LINE
{
	CHANNEL = "config_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 36;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_a20";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 37;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_a21";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 38;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_a22";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 39;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_cs_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 40;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_oe_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 41;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_reset_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 42;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "flash_rw_n";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 43;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "pld_msel0";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 44;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "pld_msel1";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 45;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "loading_led";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 46;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "user_led";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 47;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "error_led";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 48;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 84165000;
	MASTER = TRUE;
}

TIME_BAR
{
	TIME = 100000000;
	MASTER = FALSE;
}
;
上一页 12
💿 文件大小 374 K
👤 上传用户 starsrain1
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #Cyclone #FPGA #硬件描述语言
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