multiplier.vt

NC-SIM 5.40

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/27/2006 10:19:21"
                                                                                
// Verilog Test Bench (with test vectors) for design :                          multiplier
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module multiplier_vlg_vec_tst();
// constants                                           
// general purpose registers                               
reg t__reg__clk;
reg [7:0] t__reg__data_a;
reg [7:0] t__reg__data_b;
reg t__reg__rst;
// wires                                               
wire t__wire__clk;
wire [7:0] t__wire__data_a;
wire [7:0] t__wire__data_b;
wire t__wire__lock;
wire [15:0] t__wire__result_reg;
wire t__wire__rst;

// assign statements (if any)                          
assign {t__wire__clk,t__wire__data_a,t__wire__data_b,t__wire__rst} = {t__reg__clk,t__reg__data_a,t__reg__data_b,t__reg__rst};
multiplier i1 (
// port map - connection between master ports and signals/registers   
	.clk(t__wire__clk),
	.data_a(t__wire__data_a),
	.data_b(t__wire__data_b),
	.lock(t__wire__lock),
	.result_reg(t__wire__result_reg),
	.rst(t__wire__rst)
);
initial 
begin 
#1000000 $stop;
end 

// clk
always
begin
	t__reg__clk = 1'b0;
	t__reg__clk = #10000 1'b1;
	#10000;
end 

// rst
initial
begin
	t__reg__rst = 1'b0;
	t__reg__rst = #20000 1'b1;
end 
// data_a[ 7 ]
initial
begin
	t__reg__data_a[7] = 1'b0;
end 
// data_a[ 6 ]
initial
begin
	t__reg__data_a[6] = 1'b0;
end 
// data_a[ 5 ]
initial
begin
	t__reg__data_a[5] = 1'b0;
end 
// data_a[ 4 ]
initial
begin
	t__reg__data_a[4] = 1'b0;
end 
// data_a[ 3 ]
initial
begin
	t__reg__data_a[3] = 1'b0;
end 
// data_a[ 2 ]
initial
begin
	t__reg__data_a[2] = 1'b0;
	t__reg__data_a[2] = #750000 1'b1;
end 
// data_a[ 1 ]
initial
begin
	t__reg__data_a[1] = 1'b0;
	t__reg__data_a[1] = #250000 1'b1;
	t__reg__data_a[1] = #500000 1'b0;
end 
// data_a[ 0 ]
initial
begin
	t__reg__data_a[0] = 1'b1;
	t__reg__data_a[0] = #250000 1'b0;
	t__reg__data_a[0] = #250000 1'b1;
end 
// data_b[ 7 ]
initial
begin
	t__reg__data_b[7] = 1'b0;
end 
// data_b[ 6 ]
initial
begin
	t__reg__data_b[6] = 1'b0;
end 
// data_b[ 5 ]
initial
begin
	t__reg__data_b[5] = 1'b0;
end 
// data_b[ 4 ]
initial
begin
	t__reg__data_b[4] = 1'b0;
end 
// data_b[ 3 ]
initial
begin
	t__reg__data_b[3] = 1'b0;
end 
// data_b[ 2 ]
initial
begin
	t__reg__data_b[2] = 1'b0;
	t__reg__data_b[2] = #500000 1'b1;
end 
// data_b[ 1 ]
initial
begin
	t__reg__data_b[1] = 1'b1;
	t__reg__data_b[1] = #500000 1'b0;
end 
// data_b[ 0 ]
initial
begin
	t__reg__data_b[0] = 1'b0;
	t__reg__data_b[0] = #250000 1'b1;
	t__reg__data_b[0] = #250000 1'b0;
	t__reg__data_b[0] = #250000 1'b1;
end 
endmodule