multiplier.vo

NC-SIM 5.40

	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(lock));
// synopsys translate_off
defparam \lock~I .ddio_mode = "none";
defparam \lock~I .ddioinclk_input = "negated_inclk";
defparam \lock~I .dqs_delay_buffer_mode = "none";
defparam \lock~I .dqs_out_mode = "none";
defparam \lock~I .inclk_input = "normal";
defparam \lock~I .input_async_reset = "none";
defparam \lock~I .input_power_up = "low";
defparam \lock~I .input_register_mode = "none";
defparam \lock~I .input_sync_reset = "none";
defparam \lock~I .oe_async_reset = "none";
defparam \lock~I .oe_power_up = "low";
defparam \lock~I .oe_register_mode = "none";
defparam \lock~I .oe_sync_reset = "none";
defparam \lock~I .operation_mode = "output";
defparam \lock~I .output_async_reset = "none";
defparam \lock~I .output_power_up = "low";
defparam \lock~I .output_register_mode = "none";
defparam \lock~I .output_sync_reset = "none";
defparam \lock~I .sim_dqs_delay_increment = 0;
defparam \lock~I .sim_dqs_intrinsic_delay = 0;
defparam \lock~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AA8
stratixii_io \result_reg[0]~I (
	.datain(\result_reg[0]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[0]));
// synopsys translate_off
defparam \result_reg[0]~I .ddio_mode = "none";
defparam \result_reg[0]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[0]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[0]~I .dqs_out_mode = "none";
defparam \result_reg[0]~I .inclk_input = "normal";
defparam \result_reg[0]~I .input_async_reset = "none";
defparam \result_reg[0]~I .input_power_up = "low";
defparam \result_reg[0]~I .input_register_mode = "none";
defparam \result_reg[0]~I .input_sync_reset = "none";
defparam \result_reg[0]~I .oe_async_reset = "none";
defparam \result_reg[0]~I .oe_power_up = "low";
defparam \result_reg[0]~I .oe_register_mode = "none";
defparam \result_reg[0]~I .oe_sync_reset = "none";
defparam \result_reg[0]~I .operation_mode = "output";
defparam \result_reg[0]~I .output_async_reset = "none";
defparam \result_reg[0]~I .output_power_up = "low";
defparam \result_reg[0]~I .output_register_mode = "none";
defparam \result_reg[0]~I .output_sync_reset = "none";
defparam \result_reg[0]~I .sim_dqs_delay_increment = 0;
defparam \result_reg[0]~I .sim_dqs_intrinsic_delay = 0;
defparam \result_reg[0]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_Y10
stratixii_io \result_reg[1]~I (
	.datain(\result_reg[1]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[1]));
// synopsys translate_off
defparam \result_reg[1]~I .ddio_mode = "none";
defparam \result_reg[1]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[1]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[1]~I .dqs_out_mode = "none";
defparam \result_reg[1]~I .inclk_input = "normal";
defparam \result_reg[1]~I .input_async_reset = "none";
defparam \result_reg[1]~I .input_power_up = "low";
defparam \result_reg[1]~I .input_register_mode = "none";
defparam \result_reg[1]~I .input_sync_reset = "none";
defparam \result_reg[1]~I .oe_async_reset = "none";
defparam \result_reg[1]~I .oe_power_up = "low";
defparam \result_reg[1]~I .oe_register_mode = "none";
defparam \result_reg[1]~I .oe_sync_reset = "none";
defparam \result_reg[1]~I .operation_mode = "output";
defparam \result_reg[1]~I .output_async_reset = "none";
defparam \result_reg[1]~I .output_power_up = "low";
defparam \result_reg[1]~I .output_register_mode = "none";
defparam \result_reg[1]~I .output_sync_reset = "none";
defparam \result_reg[1]~I .sim_dqs_delay_increment = 0;
defparam \result_reg[1]~I .sim_dqs_intrinsic_delay = 0;
defparam \result_reg[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_R3
stratixii_io \result_reg[2]~I (
	.datain(\result_reg[2]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[2]));
// synopsys translate_off
defparam \result_reg[2]~I .ddio_mode = "none";
defparam \result_reg[2]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[2]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[2]~I .dqs_out_mode = "none";
defparam \result_reg[2]~I .inclk_input = "normal";
defparam \result_reg[2]~I .input_async_reset = "none";
defparam \result_reg[2]~I .input_power_up = "low";
defparam \result_reg[2]~I .input_register_mode = "none";
defparam \result_reg[2]~I .input_sync_reset = "none";
defparam \result_reg[2]~I .oe_async_reset = "none";
defparam \result_reg[2]~I .oe_power_up = "low";
defparam \result_reg[2]~I .oe_register_mode = "none";
defparam \result_reg[2]~I .oe_sync_reset = "none";
defparam \result_reg[2]~I .operation_mode = "output";
defparam \result_reg[2]~I .output_async_reset = "none";
defparam \result_reg[2]~I .output_power_up = "low";
defparam \result_reg[2]~I .output_register_mode = "none";
defparam \result_reg[2]~I .output_sync_reset = "none";
defparam \result_reg[2]~I .sim_dqs_delay_increment = 0;
defparam \result_reg[2]~I .sim_dqs_intrinsic_delay = 0;
defparam \result_reg[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AA9
stratixii_io \result_reg[3]~I (
	.datain(\result_reg[3]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[3]));
// synopsys translate_off
defparam \result_reg[3]~I .ddio_mode = "none";
defparam \result_reg[3]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[3]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[3]~I .dqs_out_mode = "none";
defparam \result_reg[3]~I .inclk_input = "normal";
defparam \result_reg[3]~I .input_async_reset = "none";
defparam \result_reg[3]~I .input_power_up = "low";
defparam \result_reg[3]~I .input_register_mode = "none";
defparam \result_reg[3]~I .input_sync_reset = "none";
defparam \result_reg[3]~I .oe_async_reset = "none";
defparam \result_reg[3]~I .oe_power_up = "low";
defparam \result_reg[3]~I .oe_register_mode = "none";
defparam \result_reg[3]~I .oe_sync_reset = "none";
defparam \result_reg[3]~I .operation_mode = "output";
defparam \result_reg[3]~I .output_async_reset = "none";
defparam \result_reg[3]~I .output_power_up = "low";
defparam \result_reg[3]~I .output_register_mode = "none";
defparam \result_reg[3]~I .output_sync_reset = "none";
defparam \result_reg[3]~I .sim_dqs_delay_increment = 0;
defparam \result_reg[3]~I .sim_dqs_intrinsic_delay = 0;
defparam \result_reg[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AA10
stratixii_io \result_reg[4]~I (
	.datain(\result_reg[4]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[4]));
// synopsys translate_off
defparam \result_reg[4]~I .ddio_mode = "none";
defparam \result_reg[4]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[4]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[4]~I .dqs_out_mode = "none";
defparam \result_reg[4]~I .inclk_input = "normal";
defparam \result_reg[4]~I .input_async_reset = "none";
defparam \result_reg[4]~I .input_power_up = "low";
defparam \result_reg[4]~I .input_register_mode = "none";
defparam \result_reg[4]~I .input_sync_reset = "none";
defparam \result_reg[4]~I .oe_async_reset = "none";
defparam \result_reg[4]~I .oe_power_up = "low";
defparam \result_reg[4]~I .oe_register_mode = "none";
defparam \result_reg[4]~I .oe_sync_reset = "none";
defparam \result_reg[4]~I .operation_mode = "output";
defparam \result_reg[4]~I .output_async_reset = "none";
defparam \result_reg[4]~I .output_power_up = "low";
defparam \result_reg[4]~I .output_register_mode = "none";
defparam \result_reg[4]~I .output_sync_reset = "none";
defparam \result_reg[4]~I .sim_dqs_delay_increment = 0;
defparam \result_reg[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \result_reg[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_Y5
stratixii_io \result_reg[5]~I (
	.datain(\result_reg[5]~reg0 ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(result_reg[5]));
// synopsys translate_off
defparam \result_reg[5]~I .ddio_mode = "none";
defparam \result_reg[5]~I .ddioinclk_input = "negated_inclk";
defparam \result_reg[5]~I .dqs_delay_buffer_mode = "none";
defparam \result_reg[5]~I .dqs_out_mode = "none";
defparam \result_reg[5]~I .inclk_input = "normal";
defparam \result_reg[5]~I .input_async_reset = "none";
defparam \result_reg[5]~I .input_power_up = "low";
defparam \result_reg[5]~I .input_register_mode = "none";
defparam \result_reg[5]~I .input_sync_reset = "none";
defparam \result_reg[5]~I .oe_async_reset = "none";
defparam \result_reg[5]~I