multiplier.vo

NC-SIM 5.40

// atom is at PIN_R4
stratixii_io \data_b[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[5]));
// synopsys translate_off
defparam \data_b[5]~I .ddio_mode = "none";
defparam \data_b[5]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[5]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[5]~I .dqs_out_mode = "none";
defparam \data_b[5]~I .inclk_input = "normal";
defparam \data_b[5]~I .input_async_reset = "none";
defparam \data_b[5]~I .input_power_up = "low";
defparam \data_b[5]~I .input_register_mode = "none";
defparam \data_b[5]~I .input_sync_reset = "none";
defparam \data_b[5]~I .oe_async_reset = "none";
defparam \data_b[5]~I .oe_power_up = "low";
defparam \data_b[5]~I .oe_register_mode = "none";
defparam \data_b[5]~I .oe_sync_reset = "none";
defparam \data_b[5]~I .operation_mode = "input";
defparam \data_b[5]~I .output_async_reset = "none";
defparam \data_b[5]~I .output_power_up = "low";
defparam \data_b[5]~I .output_register_mode = "none";
defparam \data_b[5]~I .output_sync_reset = "none";
defparam \data_b[5]~I .sim_dqs_delay_increment = 0;
defparam \data_b[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_Y9
stratixii_io \data_b[6]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [6]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[6]));
// synopsys translate_off
defparam \data_b[6]~I .ddio_mode = "none";
defparam \data_b[6]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[6]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[6]~I .dqs_out_mode = "none";
defparam \data_b[6]~I .inclk_input = "normal";
defparam \data_b[6]~I .input_async_reset = "none";
defparam \data_b[6]~I .input_power_up = "low";
defparam \data_b[6]~I .input_register_mode = "none";
defparam \data_b[6]~I .input_sync_reset = "none";
defparam \data_b[6]~I .oe_async_reset = "none";
defparam \data_b[6]~I .oe_power_up = "low";
defparam \data_b[6]~I .oe_register_mode = "none";
defparam \data_b[6]~I .oe_sync_reset = "none";
defparam \data_b[6]~I .operation_mode = "input";
defparam \data_b[6]~I .output_async_reset = "none";
defparam \data_b[6]~I .output_power_up = "low";
defparam \data_b[6]~I .output_register_mode = "none";
defparam \data_b[6]~I .output_sync_reset = "none";
defparam \data_b[6]~I .sim_dqs_delay_increment = 0;
defparam \data_b[6]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[6]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_T4
stratixii_io \data_b[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[7]));
// synopsys translate_off
defparam \data_b[7]~I .ddio_mode = "none";
defparam \data_b[7]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[7]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[7]~I .dqs_out_mode = "none";
defparam \data_b[7]~I .inclk_input = "normal";
defparam \data_b[7]~I .input_async_reset = "none";
defparam \data_b[7]~I .input_power_up = "low";
defparam \data_b[7]~I .input_register_mode = "none";
defparam \data_b[7]~I .input_sync_reset = "none";
defparam \data_b[7]~I .oe_async_reset = "none";
defparam \data_b[7]~I .oe_power_up = "low";
defparam \data_b[7]~I .oe_register_mode = "none";
defparam \data_b[7]~I .oe_sync_reset = "none";
defparam \data_b[7]~I .operation_mode = "input";
defparam \data_b[7]~I .output_async_reset = "none";
defparam \data_b[7]~I .output_power_up = "low";
defparam \data_b[7]~I .output_register_mode = "none";
defparam \data_b[7]~I .output_sync_reset = "none";
defparam \data_b[7]~I .sim_dqs_delay_increment = 0;
defparam \data_b[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at CLKCTRL_G1
stratixii_clkctrl \PLL|altpll_component|_clk0~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\PLL|altpll_component|_clk0 }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\PLL|altpll_component|_clk0~clkctrl ));
// synopsys translate_off
defparam \PLL|altpll_component|_clk0~clkctrl_I .clock_type = "Global Clock";
// synopsys translate_on

// atom is at DSPMULT_X28_Y5_N0
stratixii_mac_mult \MULT|lpm_mult_component|auto_generated|mac_mult2~I (
	.signa(gnd),
	.signb(gnd),
	.sourcea(gnd),
	.sourceb(gnd),
	.round(gnd),
	.saturate(gnd),
	.mode(gnd),
	.zeroacc(gnd),
	.dataa({\data_a~combout [7],\data_a~combout [6],\data_a~combout [5],\data_a~combout [4],\data_a~combout [3],\data_a~combout [2],\data_a~combout [1],\data_a~combout [0],gnd}),
	.datab({\data_b~combout [7],\data_b~combout [6],\data_b~combout [5],\data_b~combout [4],\data_b~combout [3],\data_b~combout [2],\data_b~combout [1],\data_b~combout [0],gnd}),
	.scanina(),
	.scaninb(),
	.clk({gnd,gnd,gnd,\PLL|altpll_component|_clk0~clkctrl }),
	.aclr({gnd,gnd,gnd,!\rst~clkctrl }),
	.ena({vcc,vcc,vcc,vcc}),
	.devclrn(devclrn),
	.devpor(devpor),
	.dataout(\MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus ),
	.scanouta(),
	.scanoutb());
// synopsys translate_off
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .bypass_multiplier = "no";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .dataa_clear = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .dataa_clock = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .dataa_width = 9;
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .datab_clear = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .datab_clock = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .datab_width = 9;
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .dynamic_mode = "no";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .mode_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .mode_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .output_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .output_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .round_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .round_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .saturate_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .saturate_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signa_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signa_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signa_internally_grounded = "false";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signb_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signb_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .signb_internally_grounded = "false";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .zeroacc_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_mult2~I .zeroacc_clock = "none";
// synopsys translate_on

// atom is at DSPOUT_X28_Y5_N2
stratixii_mac_out \MULT|lpm_mult_component|auto_generated|mac_out1 (
	.zeroacc(gnd),
	.zeroacc1(gnd),
	.addnsub0(vcc),
	.addnsub1(vcc),
	.round0(gnd),
	.round1(gnd),
	.saturate(gnd),
	.saturate1(gnd),
	.multabsaturate(gnd),
	.multcdsaturate(gnd),
	.signa(vcc),
	.signb(vcc),
	.mode0(gnd),
	.mode1(gnd),
	.dataa({\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT15 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT14 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT13 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT12 ,
\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT11 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT10 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT9 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT8 ,
\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT7 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT6 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT5 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT4 ,
\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT3 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT2 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT1 ,\MULT|lpm_mult_component|auto_generated|mac_mult2 ,
\MULT|lpm_mult_component|auto_generated|mac_mult2~3 ,\MULT|lpm_mult_component|auto_generated|mac_mult2~2 }),
	.datab(),
	.datac(),
	.datad(),
	.clk({gnd,gnd,gnd,\PLL|altpll_component|_clk0~clkctrl }),
	.aclr({gnd,gnd,gnd,!\rst~clkctrl }),
	.ena({vcc,vcc,vcc,vcc}),
	.devclrn(devclrn),
	.devpor(devpor),
	.accoverflow(),
	.dataout(\MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus ));
// synopsys translate_off
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub0_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub0_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub0_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub0_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub1_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .addnsub1_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .dataa_forced_to_zero = "no";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .dataa_width = 18;
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .datac_forced_to_zero = "no";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .dataout_width = 18;
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode0_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode0_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode0_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode0_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode1_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .mode1_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multabsaturate_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multabsaturate_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multabsaturate_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multabsaturate_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multcdsaturate_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multcdsaturate_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multcdsaturate_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .multcdsaturate_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .operation_mode = "output_only";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output2_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output2_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output3_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output3_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output4_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output4_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output5_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output5_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output6_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output6_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output7_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output7_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output_clear = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .output_clock = "0";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round0_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round0_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round0_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round0_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round1_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .round1_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate1_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate1_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .saturate_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signa_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signa_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signa_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signa_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signb_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signb_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signb_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .signb_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc1_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc1_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc1_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc1_pipeline_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc_clock = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc_pipeline_clear = "none";
defparam \MULT|lpm_mult_component|auto_generated|mac_out1 .zeroacc_pipeline_clock = "none";
// synopsys translate_on

// atom is at PIN_N21
stratixii_io \lock~I (
	.datain(\PLL|altpll_component|_locked ),
	.ddiodatain(gnd),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),