multiplier.vo

NC-SIM 5.40

	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [6]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[6]));
// synopsys translate_off
defparam \data_a[6]~I .ddio_mode = "none";
defparam \data_a[6]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[6]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[6]~I .dqs_out_mode = "none";
defparam \data_a[6]~I .inclk_input = "normal";
defparam \data_a[6]~I .input_async_reset = "none";
defparam \data_a[6]~I .input_power_up = "low";
defparam \data_a[6]~I .input_register_mode = "none";
defparam \data_a[6]~I .input_sync_reset = "none";
defparam \data_a[6]~I .oe_async_reset = "none";
defparam \data_a[6]~I .oe_power_up = "low";
defparam \data_a[6]~I .oe_register_mode = "none";
defparam \data_a[6]~I .oe_sync_reset = "none";
defparam \data_a[6]~I .operation_mode = "input";
defparam \data_a[6]~I .output_async_reset = "none";
defparam \data_a[6]~I .output_power_up = "low";
defparam \data_a[6]~I .output_register_mode = "none";
defparam \data_a[6]~I .output_sync_reset = "none";
defparam \data_a[6]~I .sim_dqs_delay_increment = 0;
defparam \data_a[6]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[6]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_U2
stratixii_io \data_a[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[7]));
// synopsys translate_off
defparam \data_a[7]~I .ddio_mode = "none";
defparam \data_a[7]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[7]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[7]~I .dqs_out_mode = "none";
defparam \data_a[7]~I .inclk_input = "normal";
defparam \data_a[7]~I .input_async_reset = "none";
defparam \data_a[7]~I .input_power_up = "low";
defparam \data_a[7]~I .input_register_mode = "none";
defparam \data_a[7]~I .input_sync_reset = "none";
defparam \data_a[7]~I .oe_async_reset = "none";
defparam \data_a[7]~I .oe_power_up = "low";
defparam \data_a[7]~I .oe_register_mode = "none";
defparam \data_a[7]~I .oe_sync_reset = "none";
defparam \data_a[7]~I .operation_mode = "input";
defparam \data_a[7]~I .output_async_reset = "none";
defparam \data_a[7]~I .output_power_up = "low";
defparam \data_a[7]~I .output_register_mode = "none";
defparam \data_a[7]~I .output_sync_reset = "none";
defparam \data_a[7]~I .sim_dqs_delay_increment = 0;
defparam \data_a[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AB10
stratixii_io \data_b[0]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [0]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[0]));
// synopsys translate_off
defparam \data_b[0]~I .ddio_mode = "none";
defparam \data_b[0]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[0]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[0]~I .dqs_out_mode = "none";
defparam \data_b[0]~I .inclk_input = "normal";
defparam \data_b[0]~I .input_async_reset = "none";
defparam \data_b[0]~I .input_power_up = "low";
defparam \data_b[0]~I .input_register_mode = "none";
defparam \data_b[0]~I .input_sync_reset = "none";
defparam \data_b[0]~I .oe_async_reset = "none";
defparam \data_b[0]~I .oe_power_up = "low";
defparam \data_b[0]~I .oe_register_mode = "none";
defparam \data_b[0]~I .oe_sync_reset = "none";
defparam \data_b[0]~I .operation_mode = "input";
defparam \data_b[0]~I .output_async_reset = "none";
defparam \data_b[0]~I .output_power_up = "low";
defparam \data_b[0]~I .output_register_mode = "none";
defparam \data_b[0]~I .output_sync_reset = "none";
defparam \data_b[0]~I .sim_dqs_delay_increment = 0;
defparam \data_b[0]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[0]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_W9
stratixii_io \data_b[1]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [1]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[1]));
// synopsys translate_off
defparam \data_b[1]~I .ddio_mode = "none";
defparam \data_b[1]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[1]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[1]~I .dqs_out_mode = "none";
defparam \data_b[1]~I .inclk_input = "normal";
defparam \data_b[1]~I .input_async_reset = "none";
defparam \data_b[1]~I .input_power_up = "low";
defparam \data_b[1]~I .input_register_mode = "none";
defparam \data_b[1]~I .input_sync_reset = "none";
defparam \data_b[1]~I .oe_async_reset = "none";
defparam \data_b[1]~I .oe_power_up = "low";
defparam \data_b[1]~I .oe_register_mode = "none";
defparam \data_b[1]~I .oe_sync_reset = "none";
defparam \data_b[1]~I .operation_mode = "input";
defparam \data_b[1]~I .output_async_reset = "none";
defparam \data_b[1]~I .output_power_up = "low";
defparam \data_b[1]~I .output_register_mode = "none";
defparam \data_b[1]~I .output_sync_reset = "none";
defparam \data_b[1]~I .sim_dqs_delay_increment = 0;
defparam \data_b[1]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_R5
stratixii_io \data_b[2]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [2]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[2]));
// synopsys translate_off
defparam \data_b[2]~I .ddio_mode = "none";
defparam \data_b[2]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[2]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[2]~I .dqs_out_mode = "none";
defparam \data_b[2]~I .inclk_input = "normal";
defparam \data_b[2]~I .input_async_reset = "none";
defparam \data_b[2]~I .input_power_up = "low";
defparam \data_b[2]~I .input_register_mode = "none";
defparam \data_b[2]~I .input_sync_reset = "none";
defparam \data_b[2]~I .oe_async_reset = "none";
defparam \data_b[2]~I .oe_power_up = "low";
defparam \data_b[2]~I .oe_register_mode = "none";
defparam \data_b[2]~I .oe_sync_reset = "none";
defparam \data_b[2]~I .operation_mode = "input";
defparam \data_b[2]~I .output_async_reset = "none";
defparam \data_b[2]~I .output_power_up = "low";
defparam \data_b[2]~I .output_register_mode = "none";
defparam \data_b[2]~I .output_sync_reset = "none";
defparam \data_b[2]~I .sim_dqs_delay_increment = 0;
defparam \data_b[2]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AB5
stratixii_io \data_b[3]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [3]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[3]));
// synopsys translate_off
defparam \data_b[3]~I .ddio_mode = "none";
defparam \data_b[3]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[3]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[3]~I .dqs_out_mode = "none";
defparam \data_b[3]~I .inclk_input = "normal";
defparam \data_b[3]~I .input_async_reset = "none";
defparam \data_b[3]~I .input_power_up = "low";
defparam \data_b[3]~I .input_register_mode = "none";
defparam \data_b[3]~I .input_sync_reset = "none";
defparam \data_b[3]~I .oe_async_reset = "none";
defparam \data_b[3]~I .oe_power_up = "low";
defparam \data_b[3]~I .oe_register_mode = "none";
defparam \data_b[3]~I .oe_sync_reset = "none";
defparam \data_b[3]~I .operation_mode = "input";
defparam \data_b[3]~I .output_async_reset = "none";
defparam \data_b[3]~I .output_power_up = "low";
defparam \data_b[3]~I .output_register_mode = "none";
defparam \data_b[3]~I .output_sync_reset = "none";
defparam \data_b[3]~I .sim_dqs_delay_increment = 0;
defparam \data_b[3]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_AB8
stratixii_io \data_b[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_b~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_b[4]));
// synopsys translate_off
defparam \data_b[4]~I .ddio_mode = "none";
defparam \data_b[4]~I .ddioinclk_input = "negated_inclk";
defparam \data_b[4]~I .dqs_delay_buffer_mode = "none";
defparam \data_b[4]~I .dqs_out_mode = "none";
defparam \data_b[4]~I .inclk_input = "normal";
defparam \data_b[4]~I .input_async_reset = "none";
defparam \data_b[4]~I .input_power_up = "low";
defparam \data_b[4]~I .input_register_mode = "none";
defparam \data_b[4]~I .input_sync_reset = "none";
defparam \data_b[4]~I .oe_async_reset = "none";
defparam \data_b[4]~I .oe_power_up = "low";
defparam \data_b[4]~I .oe_register_mode = "none";
defparam \data_b[4]~I .oe_sync_reset = "none";
defparam \data_b[4]~I .operation_mode = "input";
defparam \data_b[4]~I .output_async_reset = "none";
defparam \data_b[4]~I .output_power_up = "low";
defparam \data_b[4]~I .output_register_mode = "none";
defparam \data_b[4]~I .output_sync_reset = "none";
defparam \data_b[4]~I .sim_dqs_delay_increment = 0;
defparam \data_b[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_b[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on