multiplier.vo

NC-SIM 5.40

defparam \PLL|altpll_component|pll .pll_compensation_delay = 5806;
defparam \PLL|altpll_component|pll .pll_type = "fast";
defparam \PLL|altpll_component|pll .qualify_conf_done = "off";
defparam \PLL|altpll_component|pll .self_reset_on_gated_loss_lock = "off";
defparam \PLL|altpll_component|pll .simulation_type = "timing";
defparam \PLL|altpll_component|pll .switch_over_counter = 1;
defparam \PLL|altpll_component|pll .switch_over_on_gated_lock = "off";
defparam \PLL|altpll_component|pll .switch_over_on_lossclk = "off";
defparam \PLL|altpll_component|pll .switch_over_type = "manual";
defparam \PLL|altpll_component|pll .valid_lock_multiplier = 1;
defparam \PLL|altpll_component|pll .vco_center = 1490;
defparam \PLL|altpll_component|pll .vco_max = 3333;
defparam \PLL|altpll_component|pll .vco_min = 959;
// synopsys translate_on

// atom is at PIN_AB6
stratixii_io \data_a[0]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [0]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[0]));
// synopsys translate_off
defparam \data_a[0]~I .ddio_mode = "none";
defparam \data_a[0]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[0]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[0]~I .dqs_out_mode = "none";
defparam \data_a[0]~I .inclk_input = "normal";
defparam \data_a[0]~I .input_async_reset = "none";
defparam \data_a[0]~I .input_power_up = "low";
defparam \data_a[0]~I .input_register_mode = "none";
defparam \data_a[0]~I .input_sync_reset = "none";
defparam \data_a[0]~I .oe_async_reset = "none";
defparam \data_a[0]~I .oe_power_up = "low";
defparam \data_a[0]~I .oe_register_mode = "none";
defparam \data_a[0]~I .oe_sync_reset = "none";
defparam \data_a[0]~I .operation_mode = "input";
defparam \data_a[0]~I .output_async_reset = "none";
defparam \data_a[0]~I .output_power_up = "low";
defparam \data_a[0]~I .output_register_mode = "none";
defparam \data_a[0]~I .output_sync_reset = "none";
defparam \data_a[0]~I .sim_dqs_delay_increment = 0;
defparam \data_a[0]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[0]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_Y7
stratixii_io \data_a[1]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [1]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[1]));
// synopsys translate_off
defparam \data_a[1]~I .ddio_mode = "none";
defparam \data_a[1]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[1]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[1]~I .dqs_out_mode = "none";
defparam \data_a[1]~I .inclk_input = "normal";
defparam \data_a[1]~I .input_async_reset = "none";
defparam \data_a[1]~I .input_power_up = "low";
defparam \data_a[1]~I .input_register_mode = "none";
defparam \data_a[1]~I .input_sync_reset = "none";
defparam \data_a[1]~I .oe_async_reset = "none";
defparam \data_a[1]~I .oe_power_up = "low";
defparam \data_a[1]~I .oe_register_mode = "none";
defparam \data_a[1]~I .oe_sync_reset = "none";
defparam \data_a[1]~I .operation_mode = "input";
defparam \data_a[1]~I .output_async_reset = "none";
defparam \data_a[1]~I .output_power_up = "low";
defparam \data_a[1]~I .output_register_mode = "none";
defparam \data_a[1]~I .output_sync_reset = "none";
defparam \data_a[1]~I .sim_dqs_delay_increment = 0;
defparam \data_a[1]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[1]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_T10
stratixii_io \data_a[2]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [2]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[2]));
// synopsys translate_off
defparam \data_a[2]~I .ddio_mode = "none";
defparam \data_a[2]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[2]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[2]~I .dqs_out_mode = "none";
defparam \data_a[2]~I .inclk_input = "normal";
defparam \data_a[2]~I .input_async_reset = "none";
defparam \data_a[2]~I .input_power_up = "low";
defparam \data_a[2]~I .input_register_mode = "none";
defparam \data_a[2]~I .input_sync_reset = "none";
defparam \data_a[2]~I .oe_async_reset = "none";
defparam \data_a[2]~I .oe_power_up = "low";
defparam \data_a[2]~I .oe_register_mode = "none";
defparam \data_a[2]~I .oe_sync_reset = "none";
defparam \data_a[2]~I .operation_mode = "input";
defparam \data_a[2]~I .output_async_reset = "none";
defparam \data_a[2]~I .output_power_up = "low";
defparam \data_a[2]~I .output_register_mode = "none";
defparam \data_a[2]~I .output_sync_reset = "none";
defparam \data_a[2]~I .sim_dqs_delay_increment = 0;
defparam \data_a[2]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[2]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_U4
stratixii_io \data_a[3]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [3]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[3]));
// synopsys translate_off
defparam \data_a[3]~I .ddio_mode = "none";
defparam \data_a[3]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[3]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[3]~I .dqs_out_mode = "none";
defparam \data_a[3]~I .inclk_input = "normal";
defparam \data_a[3]~I .input_async_reset = "none";
defparam \data_a[3]~I .input_power_up = "low";
defparam \data_a[3]~I .input_register_mode = "none";
defparam \data_a[3]~I .input_sync_reset = "none";
defparam \data_a[3]~I .oe_async_reset = "none";
defparam \data_a[3]~I .oe_power_up = "low";
defparam \data_a[3]~I .oe_register_mode = "none";
defparam \data_a[3]~I .oe_sync_reset = "none";
defparam \data_a[3]~I .operation_mode = "input";
defparam \data_a[3]~I .output_async_reset = "none";
defparam \data_a[3]~I .output_power_up = "low";
defparam \data_a[3]~I .output_register_mode = "none";
defparam \data_a[3]~I .output_sync_reset = "none";
defparam \data_a[3]~I .sim_dqs_delay_increment = 0;
defparam \data_a[3]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[3]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_R6
stratixii_io \data_a[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[4]));
// synopsys translate_off
defparam \data_a[4]~I .ddio_mode = "none";
defparam \data_a[4]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[4]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[4]~I .dqs_out_mode = "none";
defparam \data_a[4]~I .inclk_input = "normal";
defparam \data_a[4]~I .input_async_reset = "none";
defparam \data_a[4]~I .input_power_up = "low";
defparam \data_a[4]~I .input_register_mode = "none";
defparam \data_a[4]~I .input_sync_reset = "none";
defparam \data_a[4]~I .oe_async_reset = "none";
defparam \data_a[4]~I .oe_power_up = "low";
defparam \data_a[4]~I .oe_register_mode = "none";
defparam \data_a[4]~I .oe_sync_reset = "none";
defparam \data_a[4]~I .operation_mode = "input";
defparam \data_a[4]~I .output_async_reset = "none";
defparam \data_a[4]~I .output_power_up = "low";
defparam \data_a[4]~I .output_register_mode = "none";
defparam \data_a[4]~I .output_sync_reset = "none";
defparam \data_a[4]~I .sim_dqs_delay_increment = 0;
defparam \data_a[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_Y8
stratixii_io \data_a[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_a~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(data_a[5]));
// synopsys translate_off
defparam \data_a[5]~I .ddio_mode = "none";
defparam \data_a[5]~I .ddioinclk_input = "negated_inclk";
defparam \data_a[5]~I .dqs_delay_buffer_mode = "none";
defparam \data_a[5]~I .dqs_out_mode = "none";
defparam \data_a[5]~I .inclk_input = "normal";
defparam \data_a[5]~I .input_async_reset = "none";
defparam \data_a[5]~I .input_power_up = "low";
defparam \data_a[5]~I .input_register_mode = "none";
defparam \data_a[5]~I .input_sync_reset = "none";
defparam \data_a[5]~I .oe_async_reset = "none";
defparam \data_a[5]~I .oe_power_up = "low";
defparam \data_a[5]~I .oe_register_mode = "none";
defparam \data_a[5]~I .oe_sync_reset = "none";
defparam \data_a[5]~I .operation_mode = "input";
defparam \data_a[5]~I .output_async_reset = "none";
defparam \data_a[5]~I .output_power_up = "low";
defparam \data_a[5]~I .output_register_mode = "none";
defparam \data_a[5]~I .output_sync_reset = "none";
defparam \data_a[5]~I .sim_dqs_delay_increment = 0;
defparam \data_a[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \data_a[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_T6
stratixii_io \data_a[6]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),