multiplier.vo

NC-SIM 5.40

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

// DATE "10/27/2006 10:17:36"

// 
// Device: Altera EP2S15F484C4 Package FBGA484
// 

// 
// This Verilog file should be used for NC-Verilog (Verilog) only
// 

`timescale 1 ps/ 1 ps

module multiplier (
	rst,
	clk,
	data_a,
	data_b,
	lock,
	result_reg);
input 	rst;
input 	clk;
input 	[7:0] data_a;
input 	[7:0] data_b;
output 	lock;
output 	[15:0] result_reg;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("multiplier_v.sdo");
// synopsys translate_on

wire \PLL|altpll_component|pll~CLK1 ;
wire \PLL|altpll_component|pll~CLK2 ;
wire \PLL|altpll_component|pll~CLK3 ;
wire \PLL|altpll_component|pll~CLK4 ;
wire \PLL|altpll_component|pll~CLK5 ;
wire \MULT|lpm_mult_component|auto_generated|mac_out1~0 ;
wire \MULT|lpm_mult_component|auto_generated|mac_out1~1 ;
wire \rst~combout ;
wire \rst~clkctrl ;
wire \clk~combout ;
wire \PLL|altpll_component|_locked ;
wire \PLL|altpll_component|_clk0 ;
wire \PLL|altpll_component|_clk0~clkctrl ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT1 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT2 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT3 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT4 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT5 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT6 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT7 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT8 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT9 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT10 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT11 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT12 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT13 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT14 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT15 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~2 ;
wire \MULT|lpm_mult_component|auto_generated|mac_mult2~3 ;
wire \result_reg[0]~reg0 ;
wire \result_reg[1]~reg0 ;
wire \result_reg[2]~reg0 ;
wire \result_reg[3]~reg0 ;
wire \result_reg[4]~reg0 ;
wire \result_reg[5]~reg0 ;
wire \result_reg[6]~reg0 ;
wire \result_reg[7]~reg0 ;
wire \result_reg[8]~reg0 ;
wire \result_reg[9]~reg0 ;
wire \result_reg[10]~reg0 ;
wire \result_reg[11]~reg0 ;
wire \result_reg[12]~reg0 ;
wire \result_reg[13]~reg0 ;
wire \result_reg[14]~reg0 ;
wire \result_reg[15]~reg0 ;
wire [7:0] \data_a~combout ;
wire [7:0] \data_b~combout ;

wire [5:0] \PLL|altpll_component|pll_CLK_bus ;
wire [17:0] \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus ;
wire [17:0] \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus ;

assign \PLL|altpll_component|_clk0  = \PLL|altpll_component|pll_CLK_bus [0];
assign \PLL|altpll_component|pll~CLK1  = \PLL|altpll_component|pll_CLK_bus [1];
assign \PLL|altpll_component|pll~CLK2  = \PLL|altpll_component|pll_CLK_bus [2];
assign \PLL|altpll_component|pll~CLK3  = \PLL|altpll_component|pll_CLK_bus [3];
assign \PLL|altpll_component|pll~CLK4  = \PLL|altpll_component|pll_CLK_bus [4];
assign \PLL|altpll_component|pll~CLK5  = \PLL|altpll_component|pll_CLK_bus [5];

assign \MULT|lpm_mult_component|auto_generated|mac_out1~0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [0];
assign \MULT|lpm_mult_component|auto_generated|mac_out1~1  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [1];
assign \result_reg[0]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [2];
assign \result_reg[1]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [3];
assign \result_reg[2]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [4];
assign \result_reg[3]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [5];
assign \result_reg[4]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [6];
assign \result_reg[5]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [7];
assign \result_reg[6]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [8];
assign \result_reg[7]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [9];
assign \result_reg[8]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [10];
assign \result_reg[9]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [11];
assign \result_reg[10]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [12];
assign \result_reg[11]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [13];
assign \result_reg[12]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [14];
assign \result_reg[13]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [15];
assign \result_reg[14]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [16];
assign \result_reg[15]~reg0  = \MULT|lpm_mult_component|auto_generated|mac_out1_DATAOUT_bus [17];

assign \MULT|lpm_mult_component|auto_generated|mac_mult2~2  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [0];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~3  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [1];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [2];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT1  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [3];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT2  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [4];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT3  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [5];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT4  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [6];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT5  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [7];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT6  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [8];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT7  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [9];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT8  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [10];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT9  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [11];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT10  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [12];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT11  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [13];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT12  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [14];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT13  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [15];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT14  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [16];
assign \MULT|lpm_mult_component|auto_generated|mac_mult2~DATAOUT15  = \MULT|lpm_mult_component|auto_generated|mac_mult2~I_DATAOUT_bus [17];

// atom is at PIN_N20
stratixii_io \rst~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(rst));
// synopsys translate_off
defparam \rst~I .ddio_mode = "none";
defparam \rst~I .ddioinclk_input = "negated_inclk";
defparam \rst~I .dqs_delay_buffer_mode = "none";
defparam \rst~I .dqs_out_mode = "none";
defparam \rst~I .inclk_input = "normal";
defparam \rst~I .input_async_reset = "none";
defparam \rst~I .input_power_up = "low";
defparam \rst~I .input_register_mode = "none";
defparam \rst~I .input_sync_reset = "none";
defparam \rst~I .oe_async_reset = "none";
defparam \rst~I .oe_power_up = "low";
defparam \rst~I .oe_register_mode = "none";
defparam \rst~I .oe_sync_reset = "none";
defparam \rst~I .operation_mode = "input";
defparam \rst~I .output_async_reset = "none";
defparam \rst~I .output_power_up = "low";
defparam \rst~I .output_register_mode = "none";
defparam \rst~I .output_sync_reset = "none";
defparam \rst~I .sim_dqs_delay_increment = 0;
defparam \rst~I .sim_dqs_intrinsic_delay = 0;
defparam \rst~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at CLKCTRL_G3
stratixii_clkctrl \rst~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\rst~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\rst~clkctrl ));
// synopsys translate_off
defparam \rst~clkctrl_I .clock_type = "Global Clock";
// synopsys translate_on

// atom is at PIN_N22
stratixii_io \clk~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .ddioinclk_input = "negated_inclk";
defparam \clk~I .dqs_delay_buffer_mode = "none";
defparam \clk~I .dqs_out_mode = "none";
defparam \clk~I .inclk_input = "normal";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .sim_dqs_delay_increment = 0;
defparam \clk~I .sim_dqs_intrinsic_delay = 0;
defparam \clk~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PLL_2
stratixii_pll \PLL|altpll_component|pll (
	.fbin(vcc),
	.ena(vcc),
	.clkswitch(gnd),
	.areset(!\rst~clkctrl ),
	.pfdena(vcc),
	.scanclk(gnd),
	.scanread(gnd),
	.scanwrite(gnd),
	.scandata(gnd),
	.inclk({gnd,\clk~combout }),
	.testin(),
	.activeclock(),
	.clkloss(),
	.locked(\PLL|altpll_component|_locked ),
	.scandataout(),
	.scandone(),
	.enable0(),
	.enable1(),
	.testupout(),
	.testdownout(),
	.clk(\PLL|altpll_component|pll_CLK_bus ),
	.clkbad(),
	.sclkout());
// synopsys translate_off
defparam \PLL|altpll_component|pll .bandwidth = 277008;
defparam \PLL|altpll_component|pll .bandwidth_type = "auto";
defparam \PLL|altpll_component|pll .c0_high = 4;
defparam \PLL|altpll_component|pll .c0_initial = 1;
defparam \PLL|altpll_component|pll .c0_low = 3;
defparam \PLL|altpll_component|pll .c0_mode = "odd";
defparam \PLL|altpll_component|pll .c0_ph = 0;
defparam \PLL|altpll_component|pll .c1_mode = "bypass";
defparam \PLL|altpll_component|pll .c1_ph = 0;
defparam \PLL|altpll_component|pll .c2_mode = "bypass";
defparam \PLL|altpll_component|pll .c2_ph = 0;
defparam \PLL|altpll_component|pll .c3_mode = "bypass";
defparam \PLL|altpll_component|pll .c3_ph = 0;
defparam \PLL|altpll_component|pll .charge_pump_current = 96;
defparam \PLL|altpll_component|pll .clk0_counter = "c0";
defparam \PLL|altpll_component|pll .clk0_divide_by = 1;
defparam \PLL|altpll_component|pll .clk0_duty_cycle = 50;
defparam \PLL|altpll_component|pll .clk0_multiply_by = 2;
defparam \PLL|altpll_component|pll .clk0_phase_shift = "0";
defparam \PLL|altpll_component|pll .clk1_duty_cycle = 50;
defparam \PLL|altpll_component|pll .clk1_phase_shift = "0";
defparam \PLL|altpll_component|pll .clk2_duty_cycle = 50;
defparam \PLL|altpll_component|pll .clk2_phase_shift = "0";
defparam \PLL|altpll_component|pll .clk3_duty_cycle = 50;
defparam \PLL|altpll_component|pll .clk3_phase_shift = "0";
defparam \PLL|altpll_component|pll .compensate_clock = "clk0";
defparam \PLL|altpll_component|pll .enable_switch_over_counter = "off";
defparam \PLL|altpll_component|pll .gate_lock_counter = 0;
defparam \PLL|altpll_component|pll .gate_lock_signal = "no";
defparam \PLL|altpll_component|pll .inclk0_input_frequency = 20000;
defparam \PLL|altpll_component|pll .inclk1_input_frequency = 20000;
defparam \PLL|altpll_component|pll .invalid_lock_multiplier = 5;
defparam \PLL|altpll_component|pll .loop_filter_c = 8;
defparam \PLL|altpll_component|pll .loop_filter_r = " 1.500000";
defparam \PLL|altpll_component|pll .m = 14;
defparam \PLL|altpll_component|pll .m_initial = 1;
defparam \PLL|altpll_component|pll .m_ph = 0;
defparam \PLL|altpll_component|pll .n = 1;
defparam \PLL|altpll_component|pll .operation_mode = "normal";
defparam \PLL|altpll_component|pll .pfd_max = 62500;
defparam \PLL|altpll_component|pll .pfd_min = 2000;