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;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* snds.a ARM7100 Board version 1.0 */
;/* */
;/* COMPONENT */
;/* */
;/* DESCRIPTION */
;/* */
;/* ARM7100 for KS32C5000, KS32C50100 ASSEBLER SYSTEM HEADER FILE */
;/* */
;/* AUTHOR */
;/* */
;/* Young Sun KIM, Samsung Electronics, Inc. */
;/* */
;/* DATA STRUCTURES */
;/* */
;/* */
;/* FUNCTIONS */
;/* */
;/* DEPENDENCIES */
;/* */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* Young Sun KIM 09-25-1998 Created initial version 1.0 */
;/*************************************************************************/
;/*************************************************************************/
;/* Format of the Program Status Register */
;/*************************************************************************/
;/* */
;/* 31 30 29 28 7 6 5 4 3 2 1 0 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */
;/* */
;/* Processor Mode and Mask */
;/* */
;/*************************************************************************/
;
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later
MASK_MODE EQU 0x0000003F
MODE_SVC32 EQU 0x00000013
I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled
F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled
; --- System memory locations
CM_ctl_reg EQU 0x1000000C ; Address of Core Module Control Register
Remap_bit EQU 0x04 ; Bit 2 is remap bit of CM_ctl
; --- Amount of memory (in bytes) allocated for stacks
Len_FIQ_Stack EQU 0
Len_IRQ_Stack EQU 256
Len_ABT_Stack EQU 0
Len_UND_Stack EQU 0
Len_SVC_Stack EQU 1024
; Len_USR_Stack EQU 1024
; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.
Offset_FIQ_Stack EQU 0
Offset_IRQ_Stack EQU Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack EQU Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack EQU Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack EQU Offset_UND_Stack + Len_UND_Stack
; Offset_USR_Stack EQU Offset_SVC_Stack + Len_SVC_Stack
;/*************************************************************************/
;/* SYSTEM STACK MEMORY : 8K bytes system stacks are defined at memory.a
;/*************************************************************************/
USR_STACK_SIZE EQU 1024
UDF_STACK_SIZE EQU 512
ABT_STACK_SIZE EQU 512
IRQ_STACK_SIZE EQU 2048
FIQ_STACK_SIZE EQU 2048
SUP_STACK_SIZE EQU 2048
STACK_STAR_ADDR EQU 0x800000
;/*************************************************************************/
;/* SYSTEM USER STACK MEMORY
;/*************************************************************************/
SYSTEM_SIZE EQU 1024 ; Define the system stack size
TIMER_SIZE EQU 1024 ; Define timer HISR stack size
TIMER_PRIORITY EQU 2 ; Timer HISR priority (values from
; 0 to 2, where 0 is highest)
;/*************************************************************************/
;/* SYSTEM CLOCK */
;/*************************************************************************/
MHz EQU 1000000
;#ifdef KS32C50100
fMCLK_MHz EQU 50000000 ; 50MHz, KS32C50100
;#else
;fMCLK_MHz EQU 20000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 25000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 30000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 33000000 ; 33MHz, KS32C5000
;fMCLK_MHz EQU 40000000 ; 33MHz, KS32C5000
;#endif
fMCLK EQU fMCLK_MHz/MHz
ASIC_BASE EQU 0x03ff0000
;Interrupt Control
INT_CNTRL_BASE EQU (ASIC_BASE+0x4000)
;SYSTEM MANAGER REGISTERS
ARM7_SYSCFG EQU (ASIC_BASE+0x0000)
ARM7_CLKCON EQU (ASIC_BASE+0x3000)
ARM7_EXTACON0 EQU (ASIC_BASE+0x3008)
ARM7_EXTACON1 EQU (ASIC_BASE+0x300c)
ARM7_EXTDBWTH EQU (ASIC_BASE+0x3010)
ARM7_ROMCON0 EQU (ASIC_BASE+0x3014)
ARM7_ROMCON1 EQU (ASIC_BASE+0x3018)
ARM7_ROMCON2 EQU (ASIC_BASE+0x301c)
ARM7_ROMCON3 EQU (ASIC_BASE+0x3020)
ARM7_ROMCON4 EQU (ASIC_BASE+0x3024)
ARM7_ROMCON5 EQU (ASIC_BASE+0x3028)
ARM7_DRAMCON0 EQU (ASIC_BASE+0x302c)
ARM7_DRAMCON1 EQU (ASIC_BASE+0x3030)
ARM7_DRAMCON2 EQU (ASIC_BASE+0x3034)
ARM7_DRAMCON3 EQU (ASIC_BASE+0x3038)
ARM7_REFEXTCON EQU (ASIC_BASE+0x303c)
; controller registers
ARM7_INTMODE EQU (ASIC_BASE+0x4000)
ARM7_INTPEND EQU (ASIC_BASE+0x4004)
ARM7_INTMASK EQU (ASIC_BASE+0x4008)
ARM7_INTOFFSET EQU (ASIC_BASE+0x4024)
ARM7_INTPENDTST EQU (ASIC_BASE+0x402c)
INT_DISABLE EQU 0x1fffff
ARM7_INTPRI0 EQU (ASIC_BASE+0x400C)
ARM7_INTPRI1 EQU (ASIC_BASE+0x4010)
ARM7_INTPRI2 EQU (ASIC_BASE+0x4014)
ARM7_INTPRI3 EQU (ASIC_BASE+0x4018)
ARM7_INTPRI4 EQU (ASIC_BASE+0x401C)
ARM7_INTPRI5 EQU (ASIC_BASE+0x4020)
ARM7_INTOSET_FIQ EQU (ASIC_BASE+0x4030)
ARM7_INTOSET_IRQ EQU (ASIC_BASE+0x4034)
; I/O Port Interface
ARM7_IOPMOD EQU (ASIC_BASE+0x5000)
ARM7_IOPCON EQU (ASIC_BASE+0x5004)
ARM7_IOPDATA EQU (ASIC_BASE+0x5008)
; IIC Registers
ARM7_IICCON EQU (ASIC_BASE+0xf000)
ARM7_IICBUF EQU (ASIC_BASE+0xf004)
ARM7_IICPS EQU (ASIC_BASE+0xf008)
ARM7_IICCNT EQU (ASIC_BASE+0xf00c)
RESET_ROM_START EQU 0x0
ROM_COPY_SIZE EQU 0x40000 ;256K
RESET_DRAM_START EQU 0x1000000 ;16M
;/*************************************************************************/
;/* SYSTEM MEMORY CONTROL REGISTER EQU TABLES */
;/*************************************************************************/
;
;/* -> EXTDBWTH : Memory Bus Width register */
;-------------------------------------------------------------
;
DSR0 EQU 2:SHL:0 ; ROM0, 0 : Disable
; 1 : Byte
; 2 : Half-Word
; 3 : Word
DSR1 EQU 0:SHL:2 ; ROM1
DSR2 EQU 0:SHL:4 ; ROM2
DSR3 EQU 0:SHL:6 ; ROM3
DSR4 EQU 0:SHL:8 ; ROM4
DSR5 EQU 0:SHL:10 ; ROM5
DSD0 EQU 3:SHL:12 ; DRAM0
DSD1 EQU 0:SHL:14 ; DRAM1
DSD2 EQU 0:SHL:16 ; DRAM2
DSD3 EQU 0:SHL:18 ; DRAM3
DSX0 EQU 0:SHL:20 ; EXTIO0
DSX1 EQU 0:SHL:22 ; EXTIO1
DSX2 EQU 0:SHL:24 ; EXTIO2
DSX3 EQU 0:SHL:26 ; EXTIO3
rEXTDBWTH EQU DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
;-------------------------------------------------------------
;/* -> ROMCON0 : ROM Bank0 Control register */
;-------------------------------------------------------------
ROMBasePtr0 EQU 0x000:SHL:10 ;=0x0000000
ROMEndPtr0 EQU 0x20:SHL:20 ;=0x0200000
PMC0 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page
; 0x2=8Word Page, 0x3=16Word Page
rTpa0 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
rTacc0 EQU (0x6:SHL:4) ; 0x0=Disable, 0x1=2Cycle
; 0x2=3Cycle, 0x3=4Cycle
; 0x4=5Cycle, 0x5=6Cycle
; 0x6=7Cycle, 0x7=Reserved
rROMCON0 EQU ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0
;-------------------------------------------------------------
;-------------------------------------------------------------
;/* -> ROMCON0 : ROM Bank0 Control register remap set */
;-------------------------------------------------------------
ROMBasePtr0_S EQU 0x100:SHL:10 ;=0x1000000 16M
ROMEndPtr0_S EQU 0x120:SHL:20 ;=0x1100000 17M
rROMCON0_S EQU ROMBasePtr0_S+ROMEndPtr0_S+rTacc0+rTpa0+PMC0
;-------------------------------------------------------------
;/* -> ROMCON1 : ROM Bank1 Control register */
;-------------------------------------------------------------
ROMBasePtr1 EQU 0x120:SHL:10 ;=0x1100000 18M
ROMEndPtr1 EQU 0x140:SHL:20 ;=0x1300000 20M
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