compile.cfg

来自「這是用verilog寫的一個簡單的處理器」· CFG 代码 · 共 23 行

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Entity=SAP_1_tb
Architecture=
TopLevelType=3
[file:.\src\TestBench\SAP_1_TB_runtest.do]
File Time Hi=29714063
File Time Lo=-655265968
Enabled=1
[file:.\src\TestBench\SAP_1_TB.v]
File Time Hi=29714064
File Time Lo=1008826880
STATE=Compiled
Enabled=1
Lib=sap1
[file:.\src\prom.v]
File Time Hi=29714076
File Time Lo=-449058128
Enabled=1
[file:.\src\SAP_1.v]
File Time Hi=29714076
File Time Lo=-1700056976
Enabled=1