wave11.dat

這是用verilog寫的一個簡單的處理器

$WAVE2TIMED
$ENDTIME 0
;ENDWAVE
I 0 "e#V3#regc4 01xz"
S 0 0
$SIGNAL 0 asy_rst -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
S 1 0
$SIGNAL 1 clk -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
I 1 "a#V9#[7:0]wire1 ricd7 0 e#V4#wirec4 01xz"
S 113 1
$BUS 113 8 Oreg -1 0 SIGNAL 0
I 2 "e#V4#wirec4 01xz"
S 2 2
$SIGNAL 2 "(7)" 113 0 SIGNAL 0
S 3 2
$SIGNAL 3 "(6)" 113 1 SIGNAL 0
S 4 2
$SIGNAL 4 "(5)" 113 2 SIGNAL 0
S 5 2
$SIGNAL 5 "(4)" 113 3 SIGNAL 0
S 6 2
$SIGNAL 6 "(3)" 113 4 SIGNAL 0
S 7 2
$SIGNAL 7 "(2)" 113 5 SIGNAL 0
S 8 2
$SIGNAL 8 "(1)" 113 6 SIGNAL 0
S 9 2
$SIGNAL 9 "(0)" 113 7 SIGNAL 0
$ENDTIME 0
;ENDWAVE
S 10 0
$SIGNAL 10 go -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
I 3 "a#V8#[2:0]reg1 ricd2 0 e#V3#regc4 01xz"
S 114 3
$BUS 114 3 "UUT/state" -1 0 SIGNAL 0
S 35 0
$SIGNAL 35 "(2)" 114 0 SIGNAL 0
S 36 0
$SIGNAL 36 "(1)" 114 1 SIGNAL 0
S 37 0
$SIGNAL 37 "(0)" 114 2 SIGNAL 0
$ENDTIME 0
;ENDWAVE
I 4 "a#V8#[7:0]reg1 ricd7 0 e#V3#regc4 01xz"
S 115 4
$BUS 115 8 "UUT/ACC" -1 0 SIGNAL 0
S 73 0
$SIGNAL 73 "(7)" 115 0 SIGNAL 0
S 74 0
$SIGNAL 74 "(6)" 115 1 SIGNAL 0
S 75 0
$SIGNAL 75 "(5)" 115 2 SIGNAL 0
S 76 0
$SIGNAL 76 "(4)" 115 3 SIGNAL 0
S 77 0
$SIGNAL 77 "(3)" 115 4 SIGNAL 0
S 78 0
$SIGNAL 78 "(2)" 115 5 SIGNAL 0
S 79 0
$SIGNAL 79 "(1)" 115 6 SIGNAL 0
S 80 0
$SIGNAL 80 "(0)" 115 7 SIGNAL 0
$ENDTIME 0
;ENDWAVE
S 116 1
$BUS 116 8 "UUT/PROMO" -1 0 SIGNAL 0
S 57 2
$SIGNAL 57 "(7)" 116 0 SIGNAL 0
S 58 2
$SIGNAL 58 "(6)" 116 1 SIGNAL 0
S 59 2
$SIGNAL 59 "(5)" 116 2 SIGNAL 0
S 60 2
$SIGNAL 60 "(4)" 116 3 SIGNAL 0
S 61 2
$SIGNAL 61 "(3)" 116 4 SIGNAL 0
S 62 2
$SIGNAL 62 "(2)" 116 5 SIGNAL 0
S 63 2
$SIGNAL 63 "(1)" 116 6 SIGNAL 0
S 64 2
$SIGNAL 64 "(0)" 116 7 SIGNAL 0
$ENDTIME 0
;ENDWAVE
$SIGNAL 0 asy_rst -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
$SIGNAL 1 clk -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
S 117 1
$BUS 117 8 Oreg -1 0 SIGNAL 0
$SIGNAL 2 "(7)" 117 0 SIGNAL 0
$SIGNAL 3 "(6)" 117 1 SIGNAL 0
$SIGNAL 4 "(5)" 117 2 SIGNAL 0
$SIGNAL 5 "(4)" 117 3 SIGNAL 0
$SIGNAL 6 "(3)" 117 4 SIGNAL 0
$SIGNAL 7 "(2)" 117 5 SIGNAL 0
$SIGNAL 8 "(1)" 117 6 SIGNAL 0
$SIGNAL 9 "(0)" 117 7 SIGNAL 0
$ENDTIME 0
;ENDWAVE
$SIGNAL 10 go -1 0 SIGNAL 0
$ENDTIME 0
;ENDWAVE
S 118 4
$BUS 118 8 "UUT/ACC" -1 0 SIGNAL 0
$SIGNAL 73 "(7)" 118 0 SIGNAL 0
$SIGNAL 74 "(6)" 118 1 SIGNAL 0
$SIGNAL 75 "(5)" 118 2 SIGNAL 0
$SIGNAL 76 "(4)" 118 3 SIGNAL 0
$SIGNAL 77 "(3)" 118 4 SIGNAL 0
$SIGNAL 78 "(2)" 118 5 SIGNAL 0
$SIGNAL 79 "(1)" 118 6 SIGNAL 0
$SIGNAL 80 "(0)" 118 7 SIGNAL 0
$ENDTIME 0
$ENDWAVE