c_8255.vhd

vhdl实现8255,可重用

							end if;
						end if; 
						if (EIB = '1' or EOB = '1')	then					-- PB mode 1
							if D_in(3 downto 1) = "010" then	
								INTEB <= D_in(0);							-- input/output interrupt enable 
							end if;
						end if;
					else													-- write control word
						Aout <= "00000000";
						Bout <= "00000000";
						Cout <= "00000000";
						INTEA1 <= '0';
						INTEA2 <= '0';
						INTEB <= '0';
					end if;
				when others =>
			end case;
		end if;
	end if;
end process;

Data_buf: D_out <= PA_in_int when A = "00" 
				else PB_in_int when A = "01"
				else PC_in_int when A = "10" 
				else "00000000";

Data_en: D_en <= '1' when (nCS = '0' and nRD = '0') else '0';

-- decode inputs
PC_en_in(7) <= '1' when (D_in(6) = '1'										-- PA mode 2
					or D_in(6 downto 4) = "010" 						-- PA mode 1 output
					or (D_in(6 downto 4) = "011" and D_in(3) = '0')	-- PA mode 1 input and PC(7) output
					or (D_in(6 downto 5) = "00" and D_in(3) = '0'))	-- PA mode 0 and PC(7) output 
				else '0';

PC_en_in(6) <= '1' when (D_in(6 downto 3) = "0110" 							-- PA mode 1 input and PC(6) output
						or (D_in(6 downto 5) = "00" and D_in(3) = '0'))   -- PA mode 0 and PC(6) output 
				else '0'; 

PC_en_in(5) <= '1' when (D_in(6) = '1' 										-- PA mode 2
					or D_in(6 downto 4) = "011" 						-- PA mode 1 input
					or (D_in(6 downto 4) = "010" and D_in(3) = '0')	-- PA mode 1 output and PC(5) output
					or (D_in(6 downto 5) = "00" and D_in(3) = '0')) 	-- PA mode 0 and PC(5) output 
				else '0';

PC_en_in(4) <= '1' when (D_in(6 downto 3) = "0100" 							-- PA mode 1 output and PC(4) output
					or (D_in(6 downto 5) = "00" and D_in(3) = '0')) 	-- PA mode 0 and PC(4) output
				else '0';

PC_en_in(3) <= '1' when (D_in(6) = '1' 										-- PA mode 2
					or D_in(6 downto 5) = "01" 						-- PA mode 1
					or (D_in(6 downto 5) = "00" and D_in(0) = '0')) 	-- PA mode 0 and PC(3) output
				else '0';

PC_en_in(2) <= '1' when (D_in(2) = '0' and D_in(0) = '0')					-- PB mode 0 and PC(2) output
				else '0';

PC_en_in(1) <= '1' when (D_in(2) = '1'										-- PB mode 1
					or (D_in(2) = '0' and D_in(0) = '0'))				-- PB mode 0 and PC(1) output
				else '0';
PC_en_in(0) <= '1' when (D_in(2) = '1'										-- PB mode 1
					or (D_in(2) = '0' and D_in(0) = '0'))				-- PB mode 0 and PC(0) output
				else '0';

EA_IN <= '1' when (D_in(6) = '1' or D_in(4) = '0') else '0'; 				-- PA output
EIA_IN <= '1' when (D_in(6) = '1' or D_in(6 downto 4) = "011") else '0';	-- PA mode 1 input or mode 2
EOA_IN <= '1' when (D_in(6) = '1' or D_in(6 downto 4) = "010") else '0';	-- PA mode 1 output or mode 2

EB_IN <= '1' when (D_in(1) = '0') else '0'; 								-- PB output
EIB_IN <= '1' when (D_in(2) = '1' and D_in(1) = '1') else '0';				-- PB mode 1 input
EOB_IN <= '1' when (D_in(2) = '1' and D_in(1) = '0') else '0';				-- PB mode 1 output

-- write control
write_control:process(nWR,RESET)
begin
	if RESET = '1' then
		PC_en <= "00000000";
		EA <= '0';
		EB <= '0';
		EIA <= '0';
		EIB <= '0';
		EOA <= '0';
		EOB <= '0';
	elsif nWR = '1' and nWR'event then
		if nCS = '0' and A = "11" and D_in(7) = '1' then 	-- write control word
			PC_en <= PC_en_in;
			EA <= EA_IN;
			EB <= EB_IN;
			EIA <= EIA_IN;
			EOA <= EOA_IN;
			EIB <= EIB_IN;
			EOB <= EOB_IN;
		end if;
	end if;
end process;

PA_out_int <= Aout;
PB_out_int <= Bout;
PC_out_int <= Cout;

CTRL_A(7) <= EA;
CTRL_A(6) <= EIA;
CTRL_A(5) <= EOA;
CTRL_A(4) <= nCS;
CTRL_A(3) <= nWR;
CTRL_A(2) <= nRD;
CTRL_A(1) <= A(1);
CTRL_A(0) <= A(0);

CTRL_B(7) <= EB;
CTRL_B(6) <= EIB;
CTRL_B(5) <= EOB;
CTRL_B(4) <= nCS;
CTRL_B(3) <= nWR;
CTRL_B(2) <= nRD;
CTRL_B(1) <= A(1);
CTRL_B(0) <= A(0);

end RWCtrl;

---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESCRIPTION   :  Component was generated by Aldec IP CORE Generator, version 3.0
--                  Details: 
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity C_8255_CORE is
	port(
		RESET : in STD_LOGIC;
		nCS : in STD_LOGIC;
		nRD : in STD_LOGIC;
		nWR : in STD_LOGIC;
		A : in STD_LOGIC_VECTOR (1 downto 0);
		D_in : in STD_LOGIC_VECTOR (7 downto 0);
		PA_in : in STD_LOGIC_VECTOR (7 downto 0);
		PB_in : in STD_LOGIC_VECTOR (7 downto 0);
		PC_in : in STD_LOGIC_VECTOR (7 downto 0);
		D_en : out STD_LOGIC;
		PA_en : out STD_LOGIC;
		PB_en : out STD_LOGIC;
		D_out : out STD_LOGIC_VECTOR (7 downto 0);
		PA_out : out STD_LOGIC_VECTOR (7 downto 0);
		PB_out : out STD_LOGIC_VECTOR (7 downto 0);
		PC_en : out STD_LOGIC_VECTOR (7 downto 0);
		PC_out : out STD_LOGIC_VECTOR (7 downto 0)
		);
end C_8255_CORE;

architecture C_8255_CORE_ARCH of C_8255_CORE is

signal CTRL_A : STD_LOGIC_VECTOR (7 downto 0);
signal CTRL_B : STD_LOGIC_VECTOR (7 downto 0);
signal INTEA1 : STD_LOGIC ;
signal INTEA2 : STD_LOGIC ;
signal INTEB : STD_LOGIC ;
signal PA_IN_INT : STD_LOGIC_VECTOR (7 downto 0);
signal PA_OUT_INT : STD_LOGIC_VECTOR (7 downto 0);
signal PB_IN_INT : STD_LOGIC_VECTOR (7 downto 0);
signal PB_OUT_INT : STD_LOGIC_VECTOR (7 downto 0);
signal PC_IN_INT : STD_LOGIC_VECTOR (7 downto 0);
signal PC_OUT_INT : STD_LOGIC_VECTOR (7 downto 0);

---- Component declarations -----

component GROUPA
	port (
		CTRL_A : in STD_LOGIC_VECTOR (7 downto 0);
		INTEA1 : in STD_LOGIC;
		INTEA2 : in STD_LOGIC;
		PA_in : in STD_LOGIC_VECTOR (7 downto 0);
		PA_out_int : in STD_LOGIC_VECTOR (7 downto 0);
		PC_in : in STD_LOGIC_VECTOR (7 downto 3);
		PC_out_int : in STD_LOGIC_VECTOR (7 downto 3);
		PA_en : out STD_LOGIC;
		PA_in_int : out STD_LOGIC_VECTOR (7 downto 0);
		PA_out : out STD_LOGIC_VECTOR (7 downto 0);
		PC_in_int : out STD_LOGIC_VECTOR (7 downto 3);
		PC_out : out STD_LOGIC_VECTOR (7 downto 3)
	);
end component ;

component GROUPB
	port (
		CTRL_B : in STD_LOGIC_VECTOR (7 downto 0);
		INTEB : in STD_LOGIC;
		PB_in : in STD_LOGIC_VECTOR (7 downto 0);
		PB_out_int : in STD_LOGIC_VECTOR (7 downto 0);
		PB_in_int : out STD_LOGIC_VECTOR (7 downto 0);
		PB_out : out STD_LOGIC_VECTOR (7 downto 0);
		PB_en : out STD_LOGIC;
		PC_in : in STD_LOGIC_VECTOR (2 downto 0);
		PC_out_int : in STD_LOGIC_VECTOR (2 downto 0);
		PC_in_int : out STD_LOGIC_VECTOR (2 downto 0);
		PC_out : out STD_LOGIC_VECTOR (2 downto 0)
	);
end component ;

component RWCTRL
	port (
		A : in STD_LOGIC_VECTOR (1 downto 0);
		D_in : in STD_LOGIC_VECTOR (7 downto 0);
		PA_in_int : in STD_LOGIC_VECTOR (7 downto 0);
		PB_in_int : in STD_LOGIC_VECTOR (7 downto 0);
		PC_in_int : in STD_LOGIC_VECTOR (7 downto 0);
		RESET : in STD_LOGIC;
		nCS : in STD_LOGIC;
		nRD : in STD_LOGIC;
		nWR : in STD_LOGIC;
		CTRL_A : out STD_LOGIC_VECTOR (7 downto 0);
		CTRL_B : out STD_LOGIC_VECTOR (7 downto 0);
		D_en : out STD_LOGIC;
		D_out : out STD_LOGIC_VECTOR (7 downto 0);
		INTEA1 : out STD_LOGIC;
		INTEA2 : out STD_LOGIC;
		INTEB : out STD_LOGIC;
		PA_out_int : out STD_LOGIC_VECTOR (7 downto 0);
		PB_out_int : out STD_LOGIC_VECTOR (7 downto 0);
		PC_en : out STD_LOGIC_VECTOR (7 downto 0);
		PC_out_int : out STD_LOGIC_VECTOR (7 downto 0)
	);
end component ;

	signal RESET_conv : STD_LOGIC;
	signal D_in_conv : STD_LOGIC_VECTOR(7 downto 0);
	signal A_conv : STD_LOGIC_VECTOR(1 downto 0);
	signal nCS_conv : STD_LOGIC;
	signal nRD_conv : STD_LOGIC;
	signal nWR_conv : STD_LOGIC;
	signal PA_in_conv : STD_LOGIC_VECTOR(7 downto 0);
	signal PB_in_conv : STD_LOGIC_VECTOR(7 downto 0);
	signal PC_in_conv : STD_LOGIC_VECTOR(7 downto 0);

begin

D_in_conv <= To_X01Z(D_in);
A_conv <= To_X01Z(A);
nRD_conv <= To_X01Z(nRD);
nWR_conv <= To_X01Z(nWR);
nCS_conv <= To_X01Z(nCS);
RESET_conv <= To_X01Z(RESET);
PA_in_conv <= To_X01Z(PA_in);
PB_in_conv <= To_X01Z(PB_in);
PC_in_conv <= To_X01Z(PC_in);

----  Component instantiations  ----

U0 : RWCTRL
	port map(
		A => A_conv,
		CTRL_A => CTRL_A,
		CTRL_B => CTRL_B,
		D_en => D_en,
		D_in => D_in_conv,
		D_out => D_out,
		INTEA1 => INTEA1,
		INTEA2 => INTEA2,
		INTEB => INTEB,
		PA_in_int => PA_in_int,
		PA_out_int => PA_out_int,
		PB_in_int => PB_in_int,
		PB_out_int => PB_out_int,
		PC_en => PC_en,
		PC_in_int => PC_in_int,
		PC_out_int => PC_out_int,
		RESET => RESET_conv,
		nCS => nCS_conv,
		nRD => nRD_conv,
		nWR => nWR_conv
	);

U1 : GROUPA
	port map(
		CTRL_A => CTRL_A,
		INTEA1 => INTEA1,
		INTEA2 => INTEA2,
		PA_en => PA_en,
		PA_in => PA_in_conv,
		PA_in_int => PA_in_int,
		PA_out => PA_out,
		PA_out_int => PA_out_int,
		PC_in(3) => PC_in_conv(3),
		PC_in(4) => PC_in_conv(4),
		PC_in(5) => PC_in_conv(5),
		PC_in(6) => PC_in_conv(6),
		PC_in(7) => PC_in_conv(7),
		PC_in_int(3) => PC_in_int(3),
		PC_in_int(4) => PC_in_int(4),
		PC_in_int(5) => PC_in_int(5),
		PC_in_int(6) => PC_in_int(6),
		PC_in_int(7) => PC_in_int(7),
		PC_out(3) => PC_out(3),
		PC_out(4) => PC_out(4),
		PC_out(5) => PC_out(5),
		PC_out(6) => PC_out(6),
		PC_out(7) => PC_out(7),
		PC_out_int(3) => PC_out_int(3),
		PC_out_int(4) => PC_out_int(4),
		PC_out_int(5) => PC_out_int(5),
		PC_out_int(6) => PC_out_int(6),
		PC_out_int(7) => PC_out_int(7)
	);

U2 : GROUPB
	port map(
		CTRL_B => CTRL_B,
		INTEB => INTEB,
		PB_en => PB_en,
		PB_in => PB_in_conv,
		PB_in_int => PB_in_int,
		PB_out => PB_out,
		PB_out_int => PB_out_int,
		PC_in(0) => PC_in_conv(0),
		PC_in(1) => PC_in_conv(1),
		PC_in(2) => PC_in_conv(2),
		PC_in_int(0) => PC_in_int(0),
		PC_in_int(1) => PC_in_int(1),
		PC_in_int(2) => PC_in_int(2),
		PC_out(0) => PC_out(0),
		PC_out(1) => PC_out(1),
		PC_out(2) => PC_out(2),
		PC_out_int(0) => PC_out_int(0),
		PC_out_int(1) => PC_out_int(1),
		PC_out_int(2) => PC_out_int(2)
	);

end C_8255_CORE_ARCH;

---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESCRIPTION   :  Component was generated by Aldec IP CORE Generator, version 3.0
--                  Details: 
--                  Reset (RESET) active : high
--                  Chip select (nCS) active : low
--                  Write (nWR) active : low
--                  Read (nRD) active : low
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {C_8255} architecture {C_8255_arch}}

library IEEE;
use IEEE.std_logic_1164.all;

entity C_8255 is
	port(
		RESET : in STD_LOGIC;
		nCS : in STD_LOGIC;
		nRD : in STD_LOGIC;
		nWR : in STD_LOGIC;
		A : in STD_LOGIC_VECTOR (1 downto 0);
		D : inout STD_LOGIC_VECTOR (7 downto 0);
		PA : inout STD_LOGIC_VECTOR (7 downto 0);
		PB : inout STD_LOGIC_VECTOR (7 downto 0);
		PC : inout STD_LOGIC_VECTOR (7 downto 0)
	);
end C_8255;

--}} End of automatically maintained section

architecture C_8255_arch of C_8255 is

signal D_out : STD_LOGIC_VECTOR (7 downto 0);
signal D_en : STD_LOGIC;
signal PA_out : STD_LOGIC_VECTOR (7 downto 0);
signal PA_en : STD_LOGIC;
signal PB_out : STD_LOGIC_VECTOR (7 downto 0);
signal PB_en : STD_LOGIC;
signal PC_out : STD_LOGIC_VECTOR (7 downto 0);
signal PC_en : STD_LOGIC_VECTOR (7 downto 0);


---- Component declarations -----
	component PULLUP
		port (O: out std_logic);
	end component;

	component C_8255_CORE
		port (
		RESET 	: in STD_LOGIC;
		nCS 	: in STD_LOGIC;
		nRD 	: in STD_LOGIC;
		nWR 	: in STD_LOGIC;
		A 		: in STD_LOGIC_VECTOR (1 downto 0);
		D_in 	: in STD_LOGIC_VECTOR (7 downto 0);
		D_out 	: out STD_LOGIC_VECTOR (7 downto 0);
		D_en 	: out STD_LOGIC;
		PA_in 	: in STD_LOGIC_VECTOR (7 downto 0);
		PA_out 	: out STD_LOGIC_VECTOR (7 downto 0);
		PA_en 	: out STD_LOGIC;
		PB_in 	: in STD_LOGIC_VECTOR (7 downto 0);
		PB_out 	: out STD_LOGIC_VECTOR (7 downto 0);
		PB_en 	: out STD_LOGIC;
		PC_in 	: in STD_LOGIC_VECTOR (7 downto 0);
		PC_out 	: out STD_LOGIC_VECTOR (7 downto 0);
		PC_en 	: out STD_LOGIC_VECTOR (7 downto 0)
		);
	end component ;

begin

----  Component instantiations  ----

CORE : C_8255_CORE
	port map(
		RESET 	=> RESET,
		nCS 	=> nCS,
		nRD 	=> nRD,
		nWR 	=> nWR,
		A 		=> A,
		D_in 	=> D,
		D_out 	=> D_out,
		D_en 	=> D_en,
		PA_in 	=> PA,
		PA_out 	=> PA_out,
		PA_en 	=> PA_en,
		PB_in 	=> PB,
		PB_out 	=> PB_out,
		PB_en 	=> PB_en,
		PC_in 	=> PC,
		PC_out 	=> PC_out,
		PC_en 	=> PC_en
	);

PU_PC6 : PULLUP 
	port map (O => PC(6));
PU_PC4 : PULLUP 
	port map (O => PC(4));
PU_PC2 : PULLUP 
	port map (O => PC(2));


D  <= D_out  when D_en = '1' 	 else "ZZZZZZZZ";
PA <= PA_out when PA_en = '1' 	 else "ZZZZZZZZ";
PB <= PB_out when PB_en = '1' 	 else "ZZZZZZZZ";

PC(0) 	<= PC_out(0) when PC_en(0) = '1' else 'Z';
PC(1) 	<= PC_out(1) when PC_en(1) = '1' else 'Z';
PC(2) 	<= PC_out(2) when PC_en(2) = '1' else 'Z';
PC(3) 	<= PC_out(3) when PC_en(3) = '1' else 'Z';
PC(4) 	<= PC_out(4) when PC_en(4) = '1' else 'Z';
PC(5) 	<= PC_out(5) when PC_en(5) = '1' else 'Z';
PC(6) 	<= PC_out(6) when PC_en(6) = '1' else 'Z';
PC(7) 	<= PC_out(7) when PC_en(7) = '1' else 'Z';

end C_8255_arch;