c_8255.vhd

vhdl实现8255,可重用

---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESIGN        :   C-8255
-- DESCRIPTION   :   Pull-Up Component for pre-synthesis simulation
--                   DO NOT USE FOR SYNTHESIS!
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity PULLUP is 
	port (
		O : out STD_LOGIC
	); 
end entity;

architecture PULLUP_ARCH of PULLUP is
begin
	O <= 'H';
end PULLUP_ARCH;

---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESCRIPTION   :  Component was generated by Aldec IP CORE Generator, version 3.0
--                  Details: 
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GroupA is
port(	
		CTRL_A : in STD_LOGIC_VECTOR (7 downto 0);
		INTEA1 : in STD_LOGIC;
		INTEA2 : in STD_LOGIC;
		PA_in : in STD_LOGIC_VECTOR (7 downto 0);
		PA_out_int : in STD_LOGIC_VECTOR (7 downto 0);
		PC_in : in STD_LOGIC_VECTOR (7 downto 3);
		PC_out_int : in STD_LOGIC_VECTOR (7 downto 3);
		PA_en : out STD_LOGIC;
		PA_in_int : out STD_LOGIC_VECTOR (7 downto 0);
		PA_out : out STD_LOGIC_VECTOR (7 downto 0);
		PC_in_int : out STD_LOGIC_VECTOR (7 downto 3);
		PC_out : out STD_LOGIC_VECTOR (7 downto 3)
		);
end GroupA;

architecture GroupA of GroupA is
	signal A_STB : STD_LOGIC_VECTOR(7 downto 0);
	signal pA_nOBF,pA_IBF,pA_INTR,pA_INTR1,pA_INTR2 : STD_LOGIC;
	signal nSTB,nACK: STD_LOGIC;
	signal pA_INTR1_HLP1,pA_INTR1_HLP2,pA_INTR2_HLP : STD_LOGIC;
	signal pA_nOBF_HLP : STD_LOGIC;
	signal A : STD_LOGIC_VECTOR(1 downto 0);
	signal nCS,nWR,nRD : STD_LOGIC;
	signal EA,EIA,EOA : STD_LOGIC;
	signal pA_IBF_HLP1,pA_IBF_HLP2 : STD_LOGIC;
begin

EA 	<= CTRL_A(7);
EIA <= CTRL_A(6);
EOA <= CTRL_A(5);
nCS <= CTRL_A(4);
nWR <= CTRL_A(3);
nRD <= CTRL_A(2);
A(1) <= CTRL_A(1);
A(0) <= CTRL_A(0);

nACK <= PC_in(6);
nSTB <= PC_in(4);

PA_in_int <= A_STB when EIA = '1' 								-- PA mode 1 input or mode 2
			else PA_in;

PA_out <= PA_out_int;
PA_en <= '1' when (EA = '1' and EIA = '0' and EOA = '0') 		-- PA mode 0 output
				or (EA = '1' and EIA = '0' and EOA = '1')	-- PA mode 1 output
				or (EIA = '1' and EOA = '1' and nACK = '0') 	-- PA mode 2 and data acknowledge
			else '0';

PC_in_int <= PC_in;

PC_out(7) <= pA_nOBF when EOA = '1' 
			else PC_out_int(7);

PC_out(6) <= PC_out_int(6);

PC_out(5) <= pA_IBF when EIA = '1'
			else PC_out_int(5);

PC_out(4) <= PC_out_int(4);

PC_out(3) <= pA_INTR when (EIA = '1' and EOA = '1')				-- PA mode 2
			else pA_INTR1 when (EIA = '0' and EOA = '1')			-- PA mode 1 output 
			else pA_INTR2 when (EIA = '1' and EOA = '0')			-- PA mode 1 input
			else PC_out_int(3);									-- PA mode 0 

pA_INTR <= pA_INTR1 or pA_INTR2;

-- nOBF
pA_nOBF_HLP <= EOA nand nACK;

PC7:process(pA_nOBF_HLP,nWR)
begin
	if pA_nOBF_HLP = '1' then
		pA_nOBF <= '1';	
	elsif rising_edge(nWR) then
		if nCS = '0' and A = "00" then
			pA_nOBF <= '0';
		end if;
	end if;
end process;
-- end nOBF

-- IBF
pA_IBF_HLP1_set:process(EIA,nSTB,nRD)
begin
	if EIA = '0' or nSTB = '0' then
		pA_IBF_HLP1 <= '0';
	elsif falling_edge(nRD) then
		if A = "00" and nCS = '0' then
			pA_IBF_HLP1 <= '1';
		end if;
	end if;
end process;

pA_IBF_HLP2_set:process(EIA,pA_IBF_HLP1,pA_IBF)
begin
	if EIA = '0' or pA_IBF_HLP1 = '0' then
		pA_IBF_HLP2 <= '1';
	elsif falling_edge(pA_IBF) then
		pA_IBF_HLP2 <= '0';
	end if;
end process;

pA_IBF_set:process(EIA,pA_IBF_HLP1,pA_IBF_HLP2,nRD,nSTB)
begin
	if EIA = '0' or (pA_IBF_HLP1='1' and pA_IBF_HLP2='1' and nRD='1') then
		pA_IBF <= '0';
	elsif falling_edge(nSTB) then
		pA_IBF <= '1';
	end if;
end process;
-- end IBF

-- INTR1
pA_INTR1 <= '1' when pA_INTR1_HLP1 = '1' and EOA = '1' and INTEA1 = '1'
			else '0';

pA_INTR1_HLP1_set:process(EOA,pA_INTR1_HLP2,nWR)
begin
	if EOA = '0' or pA_INTR1_HLP2 = '1' then
		pA_INTR1_HLP1 <= '1';
	elsif rising_edge(nWR) then
		if A = "00" and nCS = '0' then
			pA_INTR1_HLP1 <= '0';
		end if;
	end if;
end process;

INTR1_HLP2_set:process(nACK,nWR,nCS,A,EOA)
begin
	if EOA = '0' or (nWR = '0' and nCS = '0' and A = "00") then
		pA_INTR1_HLP2 <= '0';
	elsif rising_edge(nACK) then
		if pA_nOBF = '1' then
			pA_INTR1_HLP2 <= '1';
		end if;
	end if;
end process;
-- end INTR1

-- INTR2
pA_INTR2 <= '1' when (EIA = '1' and pA_INTR2_HLP = '1' and INTEA2 = '1') else '0';

INTR2_HLP_set:process(nSTB,EIA,nRD,nCS,A)
begin
	if EIA = '0' or (nRD = '0' and nCS = '0' and A = "00") then
		pA_INTR2_HLP <= '0';
	elsif rising_edge(nSTB) then
		if pA_IBF = '1' then
			pA_INTR2_HLP <= '1';
		end if;
	end if;
end process;
-- end INTR2

input:process(nSTB)
begin
	if rising_edge(nSTB) then
		if EIA = '1' then	 						 	-- PA mode 1 input or PA mode 2
			A_STB <= PA_in;
		end if;
	end if;
end process;

end GroupA;


---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESCRIPTION   :  Component was generated by Aldec IP CORE Generator, version 3.0
--                  Details: 
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity GroupB is
	port(
		CTRL_B : in STD_LOGIC_VECTOR (7 downto 0);
		INTEB : in STD_LOGIC;
		PB_in : in STD_LOGIC_VECTOR (7 downto 0);
		PB_out_int : in STD_LOGIC_VECTOR (7 downto 0);
		PC_in : in STD_LOGIC_VECTOR (2 downto 0);
		PC_out_int : in STD_LOGIC_VECTOR (2 downto 0);
		PB_en : out STD_LOGIC;
		PB_in_int : out STD_LOGIC_VECTOR (7 downto 0);
		PB_out : out STD_LOGIC_VECTOR (7 downto 0);
		PC_in_int : out STD_LOGIC_VECTOR (2 downto 0);
		PC_out : out STD_LOGIC_VECTOR (2 downto 0)
	);
end GroupB;

architecture GroupB of GroupB is
	signal B_STB : STD_LOGIC_VECTOR(7 downto 0);
	signal nSTB,nACK : STD_LOGIC;
	signal pB_nOBF,pB_INTR1 : STD_LOGIC;
	signal pB_IBF,pB_INTR2 : STD_LOGIC;
	signal pB_INTR1_HLP1,pB_INTR1_HLP2,pB_INTR2_HLP : STD_LOGIC;
	signal pB_nOBF_HLP : STD_LOGIC;
	signal A : STD_LOGIC_VECTOR(1 downto 0);
	signal nCS,nWR,nRD : STD_LOGIC;
	signal EB,EIB,EOB : STD_LOGIC;
	signal pB_IBF_HLP1,Pb_IBF_HLP2 : STD_LOGIC;

begin

EB  <= CTRL_B(7);
EIB <= CTRL_B(6);
EOB <= CTRL_B(5);
nCS <= CTRL_B(4);
nWR <= CTRL_B(3);
nRD <= CTRL_B(2);
A(1) <= CTRL_B(1);
A(0) <= CTRL_B(0);

nSTB <= PC_in(2);
nACK <= PC_in(2);

PB_in_int <= B_STB when EIB = '1' 					-- PB input mode 1
			else PB_in;

PB_out <= PB_out_int;

PB_en <= '1' when EB = '1' else '0';

PC_in_int <= PC_in;

PC_out(2) <= PC_out_int(2);

PC_out(1) <= pB_IBF when EIB = '1'					-- PB mode 1 input
			else pB_nOBF when EOB = '1'					-- PB mode 1 output
			else PC_out_int(1);							-- PB mode 0 and PC output

PC_out(0) <= pB_INTR2 when EIB = '1'				-- PB mode 1 input
			else pB_INTR1 when EOB = '1'				-- PB mode 1 output
			else PC_out_int(0);							-- PB mode 0 and PC output

-- nOBF
pB_nOBF_HLP <= EOB nand nACK;

PC1o:process(pB_nOBF_HLP,nWR)
begin
	if pB_nOBF_HLP = '1' then
		pB_nOBF <= '1';
	elsif rising_edge(nWR) then
		if nCS = '0' and A = "01" then
			pB_nOBF <= '0';
		end if;
	end if;
end process;
-- end nOBF

-- IBF
pB_IBF_HLP1_set:process(EIB,nSTB,nRD)
begin
	if EIB = '0' or nSTB = '0' then
		pB_IBF_HLP1 <= '0';
	elsif falling_edge(nRD) then
		if A = "01" and nCS = '0' then
			pB_IBF_HLP1 <= '1';
		end if;
	end if;
end process;

pB_IBF_HLP2_set:process(EIB,pB_IBF_HLP1,pB_IBF)
begin
	if EIB = '0' or pB_IBF_HLP1 = '0' then
		pB_IBF_HLP2 <= '1';
	elsif falling_edge(pB_IBF) then
		pB_IBF_HLP2 <= '0';
	end if;
end process;

pB_IBF_set:process(EIB,pB_IBF_HLP1,pB_IBF_HLP2,nRD,nSTB)
begin
	if EIB = '0' or (pB_IBF_HLP1='1' and pB_IBF_HLP2='1' and nRD='1') then
		pB_IBF <= '0';
	elsif falling_edge(nSTB) then
		pB_IBF <= '1';
	end if;
end process;
-- end IBF

-- INTR1
pB_INTR1 <= '1' when pB_INTR1_HLP1 = '1' and EOB = '1' and INTEB = '1'
			else '0';

pB_INTR1_HLP1_set:process(EOB,pB_INTR1_HLP2,nWR)
begin
	if EOB = '0' or pB_INTR1_HLP2 = '1' then
		pB_INTR1_HLP1 <= '1';
	elsif rising_edge(nWR) then
		if A = "01" and nCS = '0' then
			pB_INTR1_HLP1 <= '0';
		end if;
	end if;
end process;

pB_INTR1_HLP2_set:process(nACK,nWR,nCS,A,EOB)
begin
	if EOB = '0' or (nWR = '0' and nCS = '0' and A = "01") then
		pB_INTR1_HLP2 <= '0';
	elsif rising_edge(nACK) then
		if pB_nOBF = '1' then
			pB_INTR1_HLP2 <= '1';
		end if;
	end if;
end process;
-- end INTR1

-- INTR2
pB_INTR2 <= '1' when EIB = '1' and pB_INTR2_HLP = '1' and INTEB = '1' and pB_IBF = '1'
			else '0';

pB_INTR2_HLP_set:process(nSTB,EIB,nRD,nCS,A)
begin
	if EIB = '0' or (nRD = '0' and nCS = '0' and A = "01") then
		pB_INTR2_HLP <= '0';
	elsif rising_edge(nSTB) then
		pB_INTR2_HLP <= '1';
	end if;
end process;
-- end INTR2

input:process(nSTB)
begin
	if rising_edge(nSTB) then
		if EIB = '1' then					  		-- PB mode 1 input
			B_STB <= PB_in;
		end if;
	end if;
end process;
end GroupB;


---------------------------------------------------------------------------
-- Copyright (c) 2002 by Aldec, Inc. All rights reserved.
--
---------------------------------------------------------------------------
-- DESCRIPTION   :  Component was generated by Aldec IP CORE Generator, version 3.0
--                  Details: 
-- CREATED       :  2004-8-31, 22:55:15
---------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity RWCtrl is
	port(
		RESET : in STD_LOGIC;
		nCS : in STD_LOGIC;
		nRD : in STD_LOGIC;
		nWR : in STD_LOGIC;
		A : in STD_LOGIC_VECTOR(1 downto 0);
		D_in : in STD_LOGIC_VECTOR(7 downto 0);
		D_out : out STD_LOGIC_VECTOR(7 downto 0);
		D_en : out STD_LOGIC;
		PA_in_int : in STD_LOGIC_VECTOR(7 downto 0);
		PB_in_int : in STD_LOGIC_VECTOR(7 downto 0);
		PC_in_int : in STD_LOGIC_VECTOR(7 downto 0);
		PA_out_int : out STD_LOGIC_VECTOR(7 downto 0);
		PB_out_int : out STD_LOGIC_VECTOR(7 downto 0);
		PC_out_int : out STD_LOGIC_VECTOR(7 downto 0);
		PC_EN : out STD_LOGIC_VECTOR(7 downto 0);
		CTRL_A : out STD_LOGIC_VECTOR(7 downto 0);
		CTRL_B : out STD_LOGIC_VECTOR(7 downto 0);
		INTEA1 : out STD_LOGIC;
		INTEA2 : out STD_LOGIC;
		INTEB : out STD_LOGIC
		);
end RWCtrl;

architecture RWCtrl of RWCtrl is
	signal Aout,Bout,Cout,PC_en_in : STD_LOGIC_VECTOR(7 downto 0);
	signal EA,EB,EIA,EOA,EIB,EOB : STD_LOGIC;
	signal EA_IN,EB_IN,EIA_IN,EOA_IN,EIB_IN,EOB_IN : STD_LOGIC;
begin

WRITE:process(RESET,nWR)
begin
	if RESET = '1' then
		Aout 	<= "00000000";
		Bout 	<= "00000000";
		Cout 	<= "00000000";
		INTEA1 <= '0';
		INTEA2 <= '0';
		INTEB <= '0';
	elsif nWR = '1' and nWR'event then
		if nCS = '0' then
			case A is
				when "00" =>												-- write to PA
					Aout <= D_in;
				when "01" =>												-- write to PB
					Bout <= D_in;
				when "10" =>												-- write to PC
					Cout <= D_in;
				when "11" =>												-- write Control word or PC bit	set/reset 
					if D_in(7) = '0' then 									-- PCH set/reset bit
						case D_in(3 downto 1) is
							when "000" => Cout(0) <= D_in(0);
							when "001" => Cout(1) <= D_in(0);
							when "010" => Cout(2) <= D_in(0);
							when "011" => Cout(3) <= D_in(0);
							when "100" => Cout(4) <= D_in(0);
							when "101" => Cout(5) <= D_in(0);
							when "110" => Cout(6) <= D_in(0);
							when "111" => Cout(7) <= D_in(0);
							when others =>
						end case;
						if (EIA = '1' or EOA = '1')	then					-- PA mode 1 or mode 2
							if D_in(3 downto 1) = "110" then	
								INTEA1 <= D_in(0);							-- output interrupt enable 
							elsif D_in(3 downto 1) = "100" then	
								INTEA2 <= D_in(0);							-- input interrupt enable