traffic.rpt

实现得失一个交通灯。利用vhdl语言

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  37     21    B         FF   +  t        1      0   1    3    6    6    0  ewg (:14)
  39     19    B         FF   +  t        1      0   1    3    6    6    0  ewr (:16)
  40     18    B         FF   +  t        0      0   0    3    6    6    0  ewy (:15)
  36     22    B         FF   +  t        0      0   0    3    6    6    0  nsg (:11)
  41     17    B         FF   +  t        0      0   0    3    6    6    0  nsr (:13)
  38     20    B         FF   +  t        0      0   0    3    6    6    0  nsy (:12)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            e:\traffic\traffic.rpt
traffic

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                     Logic cells placed in LAB 'B'
        +----------- LC21 ewg
        | +--------- LC19 ewr
        | | +------- LC18 ewy
        | | | +----- LC22 nsg
        | | | | +--- LC17 nsr
        | | | | | +- LC20 nsy
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'B'
LC      | | | | | | | A B |     Logic cells that feed LAB 'B':
LC21 -> * * * * * * | - * | <-- ewg
LC19 -> * * * * * * | - * | <-- ewr
LC18 -> * * * * * * | - * | <-- ewy
LC22 -> * * * * * * | - * | <-- nsg
LC17 -> * * * * * * | - * | <-- nsr
LC20 -> * * * * * * | - * | <-- nsy

Pin
43   -> - - - - - - | - - | <-- clk
4    -> * * * * * * | - * | <-- clr
5    -> * * * * * * | - * | <-- em
6    -> * * * * * * | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            e:\traffic\traffic.rpt
traffic

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
em       : INPUT;
en       : INPUT;

-- Node name is 'ewg' = 'a2' 
-- Equation name is 'ewg', location is LC021, type is output.
 ewg     = DFFE( _EQ001 $  em, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ001 = !em &  en & !ewg & !ewr &  ewy & !nsg & !nsr &  nsy
         # !em & !en &  ewg
         #  em & !en & !ewg;

-- Node name is 'ewr' = 'a0' 
-- Equation name is 'ewr', location is LC019, type is output.
 ewr     = DFFE( _EQ002 $  VCC, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ002 =  en & !ewg &  ewr & !ewy &  nsg & !nsr & !nsy
         # !ewg & !ewr &  ewy & !nsg & !nsr &  nsy
         #  em &  en
         # !en & !ewr;

-- Node name is 'ewy' = 'a1' 
-- Equation name is 'ewy', location is LC018, type is output.
 ewy     = DFFE( _EQ003 $ !en, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ003 = !em &  en & !ewg &  ewr & !ewy &  nsg & !nsr & !nsy
         # !en & !ewy;

-- Node name is 'nsg' = 'a5' 
-- Equation name is 'nsg', location is LC022, type is output.
 nsg     = DFFE( _EQ004 $  VCC, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ004 = !em &  en & !ewg &  ewr & !ewy &  nsg & !nsr & !nsy
         # !em & !ewg & !ewr &  ewy & !nsg & !nsr &  nsy
         # !en & !nsg;

-- Node name is 'nsr' = 'a3' 
-- Equation name is 'nsr', location is LC017, type is output.
 nsr     = DFFE( _EQ005 $ !en, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ005 = !em &  en & !ewg & !ewr &  ewy & !nsg & !nsr &  nsy
         # !en & !nsr;

-- Node name is 'nsy' = 'a4' 
-- Equation name is 'nsy', location is LC020, type is output.
 nsy     = DFFE( _EQ006 $ !en, GLOBAL( clk), !clr,  VCC,  VCC);
  _EQ006 = !em &  en & !ewg &  ewr & !ewy &  nsg & !nsr & !nsy
         # !en & !nsy;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     e:\traffic\traffic.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,321K