it51_core.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

            when "10001110" => SFR_RData <= CKCON; -- 8E
            when "10010010" => SFR_RData <= MPAGE; -- 92
            when "11010000" => SFR_RData <= PSW & PSW0;
            when "11100000" => SFR_RData <= ACC;
            when "11110000" => SFR_RData <= B;
            when "10000001" => SFR_RData <= std_logic_vector(SP);
            when "11111000" => SFR_RData <= EIP; -- F8
            when others =>     SFR_RData <= SFR_RData_Ext;
        end case;
    end process;

    -- SFR_Rd_i
    process (cInst, Second_Cycle, Int_AddrA, Last_Cycle, cInst_is_DR,
             cInst_is_Ri, cInst_is_PUSH, iSP, First_Cycle, PCPause,
             cInst_is_JB, cInst_is_JBC )
    begin
        SFR_Rd_i <= '0';
        if cInst(7 downto 3) = "10101"  -- MOV Rn, DA
        then
            if First_Cycle and not PCPause and Int_AddrA(7) = '1' then
                SFR_Rd_i <= '1';
            end if;
        elsif cInst = "10000101" or   -- MOV DA, DA
              cInst = "10110101" or   -- CJNE
              cInst_is_JB or  -- JB
              cInst_is_JBC    -- JBC
        then
            if Second_Cycle and Int_AddrA(7) = '1' then
                SFR_Rd_i <= '1';
            end if;
        else
            if Last_Cycle and Int_AddrA(7) = '1' and
               cInst_is_DR and not cInst_is_Ri and cInst(7 downto 3) /= "10001" and
              (not cInst_is_PUSH or (cInst_is_PUSH and Int_AddrA/=iSP)) then
                SFR_Rd_i <= '1';
            end if;
        end if;
    end process;

    -- SFR_Wr_i
    process (Last_Cycle, Int_AddrA, cInst_is_DW, CInst_is_IW, CInst_is_PUSH)
    begin
        if Last_Cycle  and Int_AddrA(7) = '1' and cInst_is_DW
           and not CInst_is_IW and not CInst_is_PUSH then
            SFR_Wr_p <= '1';
        else
            SFR_Wr_p <= '0';
        end if;
    end process;

    process (Clk, Rst_n)
    begin
        if Rst_n = '0' then
            SFR_Wr_i <= '0';
        elsif Clk'event and Clk = '1' then
            SFR_Wr_i <= SFR_Wr_p;
        end if;
    end process;

    -- SFR_RData_r
    process (Clk, Rst_n)
    begin
        if Rst_n = '0' then
            SFR_RData_r <= (others => '0');
        elsif Clk'event and Clk = '1' then
            SFR_RData_r <= SFR_RData;
        end if;
    end process;

    ----------------------------------------------------------------------------
    -- External Memory Access
    RAM_Cycle <= '1' when cInst(7 downto 5) = "111" and
                          cInst(3 downto 2) = "00"  and
                          cInst(1 downto 0) /= "01" and
                          PCPaused(0) = '0' else '0';
    RAM_Rd    <= RAM_Rd_i;
    RAM_Wr    <= RAM_Wr_i;
    RAM_WData <= ACC;
    process (Rst_n, Clk)
        variable tmp : unsigned(15 downto 0);
    begin
        if Rst_n = '0' then
            RAM_Rd_i <= '0';
            RAM_Wr_i <= '0';
        elsif Clk'event and Clk = '1' then
            RAM_Wr_i <= '0';
            if cInst_is_MOVX_Write and not PCPause then
                RAM_Wr_i <= '1';
            end if;
            RAM_Rd_i <= '0';
            if cInst_is_MOVX_Read and not PCPause and Ready then
                RAM_Rd_i <= '1';
            end if;
        end if;
    end process;

    process (cInst, MPAGE, DPTR0, DPTR1, DPS,
             Int_AddrA_r, SFR_Wr_i, Res_Bus, INC_DPTR, Mem_A,
			 Mem_Wr, PSW, Mem_Din)
    begin
        if DPS_SEL = '0' then
            RAM_Addr <= DPTR0;
        else
            RAM_Addr <= DPTR1;
        end if;
        if cInst(1) = '0' then
            -- DPS_SEL Cgange
            if SFR_Wr_i = '1' and Int_AddrA_r = "10000110" then
                if Res_Bus(0) = '0' then
                    RAM_Addr <= DPTR0;
                else
                    RAM_Addr <= DPTR1;
                end if;
            end if;
            if SFR_Wr_i = '1' and Int_AddrA_r = "10000010" then
                RAM_Addr(7 downto 0) <= Res_Bus;
            end if;
            if SFR_Wr_i = '1' and Int_AddrA_r = "10000011" then
                RAM_Addr(15 downto 8) <= Res_Bus;
            end if;
            -- 10100011 1 INC   DPTR
            if INC_DPTR then
                if DPS_SEL = '0' then
                    RAM_Addr <= DPTR0 + 1;
                else
                    RAM_Addr <= DPTR1 + 1;
                end if;
            end if;
        else
            RAM_Addr <= MPAGE & Mem_A;
            if SFR_Wr_i = '1' and Int_AddrA_r = "10100000" then
                RAM_Addr(15 downto 8) <= Res_Bus;
            end if;
            if Mem_Wr = '1' and
               Int_AddrA_r = ("000" & PSW(4 downto 3) & "00" & cInst(0)) then
                RAM_Addr(7 downto 0) <= Mem_Din;
            end if;
        end if;
    end process;

    ----------------------------------------------------------------------------
    -- Internal SP (iSP)
    process (SFR_Wr_i, Int_AddrA_r, Res_Bus, SP)
    begin
        if SFR_Wr_i = '1' and Int_AddrA_r = "10000001" then
            iSP <= std_logic_vector(Res_Bus);
        else
            iSP <= SP;
        end if;
    end process;
    -- SP
    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            SP <= "00000111";
        elsif Clk'event and Clk = '1' then
            if SFR_Wr_i = '1' and Int_AddrA_r = "10000001" then
                SP <= Res_Bus;
            end if;
            if Ready then
                if (cInst_is_RET or cInst_is_RETI) and not PCPause then
                    SP <= SP - 2;
                end if;
                if (cInst_is_LCALL or cInst_is_ACALL or ICall) and Last_Cycle then
                    -- LCALL, ACALL, ICall
                    SP <= SP + 2;
                end if;
                if cInst_is_PUSH and PCPaused(0) = '1' then
                    -- 11000000 2 PUSH  data addr       INC SP: MOV "@SP",<src>
                    SP <= SP + 1;
                end if;
                if cInst_is_POP and Last_Cycle then
                    -- 11010000 2 POP   data addr       MOV <dest>,"@SP": DEC SP
                    SP <= SP - 1;
                end if;
            end if;
        end if;
    end process;

    ----------------------------------------------------------------------------
    -- Internal Memory Access
    --   Int_Addr_A
    process (nInst, ICall, cInst, cInst1, cInst2, PCPaused, PCPause,
             First_Cycle, Second_Cycle, Third_Cycle, PSW, Mem_A,
             iSP, Old_Mem_A, Ready, Int_AddrA_r, cInst_is_LCALL,
			 cInst_is_PUSH, Second_Cycle, cInst_is_POP, cInst_is_RET,
			 cInst_is_RETI, cInst_is_ACALL, cInst_is_Ri, cInst_is_Rn,
			 cInst_is_CJNE, cInst_is_7x, cInst_is_8x, cInst_is_Ax,
			 cInst_is_x3, cInst_is_x5
			 )
    begin

        Int_AddrA <= "--------";
        Mem_A_Rd  <= '0';
        if cInst(3 downto 0) = "0000" or
          (cInst(3 downto 0) = "0010" and (cInst(7) = '1' or cInst(6 downto 4) = "111")) then
            if cInst1(7) = '0' then
                Int_AddrA <= "0010" & cInst1(6 downto 3);
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= "1" & cInst1(6 downto 3) & "000"; -- BitAddress
                Mem_A_Rd  <= '1';
            end if;
        else
            Int_AddrA <= cInst1;
            Mem_A_Rd  <= '1';
        end if;

        if cInst_is_LCALL or ICall then
            if First_Cycle then
                Int_AddrA <= std_logic_vector(iSP + 1);
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= std_logic_vector(iSP + 2);
                Mem_A_Rd  <= '1';
            end if;
        end if;

        if cInst_is_PUSH then
            -- 11000000 2 PUSH  data addr       INC SP: MOV "@SP",<src>
            if Second_Cycle then
                Int_AddrA <= std_logic_vector(iSP);
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= cInst1;
                Mem_A_Rd  <= '1';
            end if;
        end if;

        if cInst_is_POP then
            -- 11010000 2 POP   data addr       MOV <dest>,"@SP": DEC SP
            if Second_Cycle then
                Int_AddrA <= cInst1;
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= std_logic_vector(iSP);
                Mem_A_Rd  <= '1';
            end if;
        end if;

        if (cInst_is_RET or cInst_is_RETI) and not PCPause then
            Int_AddrA <= std_logic_vector(iSP);
            Mem_A_Rd  <= '1';
        end if;

        if (cInst_is_RET or cInst_is_RETI) and PCPause then
            Int_AddrA <= std_logic_vector(iSP - 1);
            Mem_A_Rd  <= '1';
        end if;

        if cInst_is_ACALL then
            -- ACALL
            if First_Cycle then
                Int_AddrA <= std_logic_vector(iSP + 1);
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= std_logic_vector(iSP + 2);
                Mem_A_Rd  <= '1';
            end if;

        elsif cInst_is_x5 then
            if cInst_is_8x and Third_Cycle then
                Int_AddrA <= cInst2;
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= cInst1;
                Mem_A_Rd  <= '1';
            end if;
        elsif cInst_is_Ri then     -- @Ri

            if PCPaused(0) = '0' then
                Int_AddrA <= "000" & PSW(4 downto 3) & "00" & cInst(0);
                Mem_A_Rd  <= '1';
            else
                Int_AddrA <= Mem_A;
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_CJNE and Second_Cycle then -- CJNE
                Int_AddrA <= Mem_A;
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_CJNE and First_Cycle then -- CJNE
                Int_AddrA <= "000" & PSW(4 downto 3) & "00" & cInst(0);
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_8x and Second_Cycle then -- MOV
                Int_AddrA <= cInst1;
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_Ax and First_Cycle and not PCPause then -- MOV
                Int_AddrA <= nInst;
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_Ax and Second_Cycle then
                Int_AddrA <= Old_Mem_A;
                Mem_A_Rd  <= '1';
            end if;

            if cInst_is_7x and Second_Cycle then
                Int_AddrA <= Int_AddrA_r;
                Mem_A_Rd  <= '1';
            end if;

        elsif cInst_is_x3 then
            Int_AddrA <= cInst1;
            Mem_A_Rd  <= '1';
        elsif cInst_is_Rn then -- Rn
            Mem_A_Rd  <= '1';
            Int_AddrA <= "000" & PSW(4 downto 3) & cInst(2 downto 0);
            if cInst_is_8x and Second_Cycle then
                Int_AddrA <= cInst1;
            end if;
            if cInst_is_Ax and First_Cycle then
                Int_AddrA <= nInst;
            end if;
        end if;

        if not Ready then
            Int_AddrA <= Int_AddrA_r;
            Mem_A_Rd  <= '1';
        end if;
    end process;

    -- Int_AddrA_r
    process (Clk, Rst_n)
    begin
        if Rst_n = '0' then
            Int_AddrA_r <= (others => '0');
        elsif Clk'event and Clk = '1' then
            Int_AddrA_r <= Int_AddrA;
        end if;
    end process;
    ----------------------------------------------------------------------------