it51_core.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

            PC_Plus_cInst1 <= (others => '0');
        elsif Clk'event and Clk = '1' then
            if Ready then
                if First_Cycle then
                    PC_Plus_cInst1 <= std_logic_vector(conv_unsigned(
                                            signed(nPC) + signed(nInst), 16));
                else
                    PC_Plus_cInst1 <= std_logic_vector(conv_unsigned(
                                            signed(nPC) + signed(cInst1), 16));
                end if;
            end if;
        end if;
    end process;

    -- PC_Plus_cInst2
    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            PC_Plus_cInst2 <= (others => '0');
        elsif Clk'event and Clk = '1' then
            if Ready then
                if Second_Cycle then
                    PC_Plus_cInst2 <= std_logic_vector(conv_unsigned(
                                            signed(nPC) + signed(nInst), 16));
                else
                    PC_Plus_cInst2 <= std_logic_vector(conv_unsigned(
                                            signed(nPC) + signed(cInst2), 16));
                end if;
            end if;
        end if;
    end process;

    -- PCPaused
    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            PCPaused <= (others => '0');
        elsif Clk'event and Clk = '1' then
            if Ready then
                if PCPause then
                    PCPaused <= PCPaused + 1;
                else
                    PCPaused <= (others => '0');
                end if;
            end if;
        end if;
    end process;

    -- oPC
    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            oPC      <= (others => '0');
        elsif Clk'event and Clk = '1' then
            if Ready and cInst_is_MOVC and  First_Cycle then -- MOVC
                oPC <= PC;
            end if;
        end if;
    end process;

    ----------------------------------------------------------------------------
    -- Cycle
    Last_Cycle   <= true when ICall and Third_Cycle else
             false when ICall else
             true when cInst_MCode(1 downto 0)=FCycle and Ready else false;

    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            FCycle       <= "01";
        elsif Clk'event and Clk = '1' then
            if Ready then
                if not PCPause then
                    if Last_Cycle then
                        FCycle <= "01";
                    else
                        FCycle <= FCycle + 1;
                    end if;
                end if;
            end if;
        end if;
    end process;

--    process (Rst_n, Clk)
--    begin
--        if Rst_n = '0' then
--            First_Cycle  <= true;
--            Second_Cycle <= false;
--            Third_Cycle  <= false;
--        elsif Clk'event and Clk = '1' then
--            if Ready then
--                if not PCPause then
--                    if Last_Cycle then
--                        First_Cycle  <= true;
--                        Second_Cycle <= false;
--                        Third_Cycle  <= false;
--                    else
--                        if FCycle = "01" then
--                            First_Cycle  <= false;
--                            Second_Cycle <= true;
--                            Third_Cycle  <= false;
--                        end if;
--                        if FCycle = "10" then
--                            First_Cycle  <= false;
--                            Second_Cycle <= false;
--                            Third_Cycle  <= true;
--                        end if;
--                    end if;
--                end if;
--            end if;
--        end if;
--    end process;

    First_Cycle  <= (FCycle="01");
    Second_Cycle <= (FCycle="10");
    Third_Cycle  <= (FCycle="11");

    ----------------------------------------------------------------------------
    -- NPC (Next PC)

    DPTR0_Plus_ACC <= DPTR0 + ACC;
    DPTR1_Plus_ACC <= DPTR1 + ACC;

    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            IRQ_Entry <= (others => '0');
        elsif Clk'event and Clk = '1' then
            IRQ_Entry <= "0000000000000011";                                -- INT0
            if    Int_Trig_r(1) = '1' then IRQ_Entry <= "0000000000001011"; -- TF0
            elsif Int_Trig_r(2) = '1' then IRQ_Entry <= "0000000000010011"; -- INT1
            elsif Int_Trig_r(3) = '1' then IRQ_Entry <= "0000000000011011"; -- TF1
            elsif Int_Trig_r(4) = '1' then IRQ_Entry <= "0000000000100011"; -- TI_0 / RI_0
            elsif Int_Trig_r(5) = '1' then IRQ_Entry <= "0000000000101011"; -- TF2
            elsif Int_Trig_r(6) = '1' then IRQ_Entry <= "0000000000110011"; -- TI_1
            elsif Int_Trig_r(7) = '1' then IRQ_Entry <= "0000000001000011"; -- INT2
            elsif Int_Trig_r(8) = '1' then IRQ_Entry <= "0000000001001011"; -- INT3
            elsif Int_Trig_r(9) = '1' then IRQ_Entry <= "0000000001010011"; -- INT4
            elsif Int_Trig_r(10)= '1' then IRQ_Entry <= "0000000001011011"; -- INT5
            end if;
        end if;
    end process;

    process (PC, Rst_r_n, Ready, RET_r, Mem_A, Old_Mem_A, ICALL, Second_Cycle,
             Int_Trig_r, Ri_Stall, PSW_Stall, PC_Plus_1, cInst, First_Cycle,
             PCPaused, Div_Rdy, ACC, OPC, DPS_SEL, DPTR0_Plus_ACC, DPTR1_Plus_ACC,
             Third_Cycle, Next_PSW7, PC_Plus_cInst1, Next_ACC_Z, DJNZ, RW_Stall,
             Bit_Pattern, OP_A, PC_Plus_cInst2, CJNE, DJNZ, cInst1, nInst,
             DPS, cInst_is_Ri, IRQ_Entry,
             cInst_is_JC, cInst_is_JNC, cInst_is_DIV,
             cInst_is_POP, cInst_is_PUSH, cInst_is_RET, cInst_is_RETI,
             cInst_is_JB, cInst_is_JBC, cInst_is_JNB, cInst_is_JZ, cInst_is_JNZ,
             cInst_is_SJMP, cInst_is_MOVC, cInst_is_AJMP, cInst_is_ACALL,
             cInst_is_LJMP, cInst_is_LCALL, cInst_is_JMP_A_DPTR,
             cInst_is_CJNE, cInst_is_DJNE, cInst_is_DJNZ
			 )
    begin
        NPC     <= PC;
        J_Skip  <= false;
        PCPause <= false;

        if Rst_r_n = '0' then
            NPC <= (others => '0');
        elsif not Ready then
            NPC <= PC;
        elsif RET_r = '1' then
            NPC <= (Mem_A & Old_Mem_A);
        elsif ICALL then
            NPC <= PC_Plus_1;
            if Second_Cycle then
                NPC <= IRQ_Entry;
            end if;
--        elsif Ri_Stall or PSW_Stall or RW_Stall then
--            NPC <= PC_Plus_1;
        else
            if not Ri_Stall and not PSW_Stall and not RW_Stall then
                NPC <= PC_Plus_1;
            end if;
            if cInst_is_Ri and PCPaused(0) = '0' and First_Cycle then
                PCPause <= true;
                NPC     <= PC;
            end if;
--            case conv_integer(cInst) is
--                when 16#C0# | 16#D0#=> -- PUSH/POP
--                    if First_Cycle and PCPaused(0) = '0' then
--                        PCPause <= true;
--                        NPC     <= PC;
--                    end if;
--                when 16#84# => -- DIV
--                    if PCPaused(3 downto 1) = "000" or Div_Rdy = '0' then
--                        PCPause <= true;
--                        NPC     <= PC;
--                    end if;
--                when 16#22# | 16#32# => -- RET, RETI
--                    J_Skip <= true;
--                    if First_Cycle and PCPaused(0) = '0' then
--                        PCPause <= true;
--                        NPC     <= PC;
--                    end if;
--                when 16#83# | 16#93# => -- MOVC
--                    if Second_Cycle then
--                        if cInst(4) = '0' then
--                            NPC <= ACC + OPC;
--                        else
--                            if DPS_SEL = '0' then
--                                NPC <= DPTR0_Plus_ACC;
--                            else
--                                NPC <= DPTR1_Plus_ACC;
--                            end if;
--                        end if;
--                    elsif Third_Cycle then
--                        NPC <= OPC;
--                        J_Skip <= true;
--                    end if;
--                when 16#40# => -- JC
--                    if Next_PSW7 = '1' and Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#50# => -- JNC
--                    if Next_PSW7 = '0' and Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#60# => -- JZ
--                    if Next_ACC_Z = '1' and Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#70# => -- JNZ
--                    if Next_ACC_Z = '0' and Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#D8# to 16#DF# => --DJNZ (2 Byte)
--                    if DJNZ = '1' and Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#80# => -- SJMP
--                    if Second_Cycle then
--                        NPC    <= PC_Plus_cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#20# | 16#10# => -- JB, JBC
--                    if Third_Cycle and (Bit_Pattern and Op_A) /= "00000000" then
--                        NPC <= PC_Plus_cInst2;
--                        J_Skip <= true;
--                    end if;
--                when 16#30# =>-- JNB
--                    if Third_Cycle and (Bit_Pattern and Op_A) = "00000000" then
--                        NPC <= PC_Plus_cInst2;
--                        J_Skip <= true;
--                    end if;
--                when 16#B4# to 16#BF# => -- CJNE
--                    PCPause <= false;
--                    NPC     <= PC;
--                    if not Ri_Stall and not PSW_Stall and not RW_Stall then
--                         NPC <= PC_Plus_1;
--                    end if;
--                    if Third_Cycle and CJNE = '1' then -- CJNE
--                        NPC <= PC_Plus_cInst2;
--                        J_Skip <= true;
--                    end if;
--                when 16#D5# => -- DJNE (3 byte)
--                    if Third_Cycle and DJNZ = '1' then -- DJNZ
--                        NPC <= PC_Plus_cInst2;
--                        J_Skip <= true;
--                    end if;
--                when 16#01# | 16#21# | 16#41# |16#61# |
--	                 16#81# | 16#A1# | 16#C1# |16#E1# |  -- AJMP
--	                 16#11# | 16#31# | 16#51# |16#71# |
--	                 16#91# | 16#B1# | 16#D1# |16#F1# => -- ACALL
--	                if Second_Cycle then
--                        NPC(15 downto 11) <= PC(15 downto 11);
--                        NPC(10 downto  8) <= cInst(7 downto 5);
--                        NPC( 7 downto  0) <= cInst1;
--                        J_Skip <= true;
--                    end if;
--                when 16#02# | 16#12# => -- LJMP, LCALL
--                    if Second_Cycle then
--                        NPC(15 downto 8) <= cInst1;
--                        NPC( 7 downto 0) <= nInst;
--                    end if;
--                when 16#73# => -- JMP @A+DPTR
--                    if DPS_SEL = '0' then
--                        NPC <= DPTR0_Plus_ACC;
--                    else
--                        NPC <= DPTR1_Plus_ACC;
--                    end if;
--                    J_Skip <= true;
--                when others =>
--                    null;
--            end case;

---
            if cInst_is_CJNE then
                PCPause <= false;
                NPC     <= PC;
                if not Ri_Stall and not PSW_Stall and not RW_Stall then
                     NPC <= PC_Plus_1;
                end if;
                if Third_Cycle and CJNE = '1' then -- CJNE
                    NPC <= PC_Plus_cInst2;
                    J_Skip <= true;
                end if;
            end if;

            if cInst_is_JMP_A_DPTR then
                if DPS_SEL = '0' then
                    NPC <= DPTR0_Plus_ACC;
                else
                    NPC <= DPTR1_Plus_ACC;
                end if;
                J_Skip <= true;
            end if;

            if cInst_is_DJNE then
                if DJNZ = '1' and Third_Cycle then -- DJNZ
                    NPC <= PC_Plus_cInst2;
                    J_Skip <= true;
                end if;
            end if;

            if cInst_is_DJNZ then
                if DJNZ = '1' and Second_Cycle then
                    NPC    <= PC_Plus_cInst1;
                    J_Skip <= true;
                end if;
            end if;

            if cInst_is_JB or cInst_is_JBC then
                if Third_Cycle and (Bit_Pattern and Op_A) /= "00000000" then
                    NPC <= PC_Plus_cInst2;
                    J_Skip <= true;
                end if;
            end if;