it51_core.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

-------------------------------------------------------------------------------
--   IT51 (Improved-T51)                                                     --
--                                                                           --
--   VERSION: 030723                                                         --
--                                                                           --
--   Contact: [e-mail]                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
--  Copyright (c) 2001-2002 Daniel Wallner ([e-mail])             --
--                          Yung-Fu Chen ([e-mail])           --
--                                                                           --
-------------------------------------------------------------------------------
--  FETURE                                                                   --
--     . IT51_top interface is similar to synopsys DW8051                    --
--     . High-Performance 1-Cycle 8051                                       --
--     . instruction compatible with standard DW8051                         --
--     . 256 byte internal data memory                                       --
--     . up to 64KB external data memory                                     --
--     . up to 64KB internal program memory                                  --
--     . export sfr-bus                                                      --
--     . no dual-port memory used                                            --
--     . no watch-dog timer                                                  --
--     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
--     . sleep mode support, refer to DW8051                                 --
--     . no stop mode                                                        --
--     . six external interrupt, refer to DW8051                             --
--     . pass all DW8051 test-pattern                                        --
--     . UART/Timer are not fully tested yet                                 --
--     . no internal tri-state bus                                           --
--     . 2-Cycle MUL Instruction                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51_top (Interface Compatible with Synopsys DW8051)                     --
--     |                                                                     --
--     +-- IT51_core (Control Unit)                                          --
--     |       |                                                             --
--     |       +-- IT51_ALU (ALU)                                            --
--     |               |                                                     --
--     |               +-- IT51_MD (MUL/DIV)                                 --
--     |                                                                     --
--     +-- IT51_Glue (Glue Logic)                                            --
--     |                                                                     --
--     +-- IT51_TC01 (Timer/Counter-1)                                       --
--     |                                                                     --
--     +-- IT51_TC2 (Timer/Counter-2)                                        --
--     |                                                                     --
--     +-- IT51_UART (UART)                                                  --
--                                                                           --
-------------------------------------------------------------------------------

-- ============================================================================
-- The original T51 license is listed below:
-- ============================================================================
--
-- 8051 compatible microcontroller core
--
-- Version : 0218
--
-- Copyright (c) 2001-2002 Daniel Wallner ([e-mail])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--	http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- ============================================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.IT51_Pack.all;

entity IT51_core is
    port(
        Clk           : in  std_logic;
        Rst_n         : in  std_logic;
        Idle_n        : in  std_logic;
        ROM_Addr      : out std_logic_vector(15 downto 0);
        ROM_Data      : in  std_logic_vector(7 downto 0);
        RAM_Addr      : out std_logic_vector(15 downto 0);
        RAM_RData     : in  std_logic_vector(7 downto 0);
        RAM_WData     : out std_logic_vector(7 downto 0);
        RAM_Cycle     : out std_logic;
        RAM_Rd        : out std_logic;
        RAM_Wr        : out std_logic;
        iRAM_Addr     : out std_logic_vector(7 downto 0);
        iRAM_Rd       : out std_logic;
        iRAM_Wr       : out std_logic;
        iRAM_RData    : in  std_logic_vector(7 downto 0);
        iRAM_WData    : out std_logic_vector(7 downto 0);
        Int_Trig      : in  std_logic_vector(10 downto 0);
        Int_Acc       : out std_logic_vector(10 downto 0);
        SFR_Rd        : out std_logic;
        SFR_Wr        : out std_logic;
        SFR_Addr      : out std_logic_vector(6 downto 0);
        SFR_WData     : out std_logic_vector(7 downto 0);
        SFR_RData_Ext : in  std_logic_vector(7 downto 0)
    );
end IT51_core;

architecture rtl of IT51_core is

    -- Registers
    signal  ACC             : std_logic_vector(7 downto 0);
    signal  B               : std_logic_vector(7 downto 0);
    signal  PSW             : std_logic_vector(7 downto 1); -- Bit 0 is parity
    signal  PSW0            : std_logic;
    signal  IP              : std_logic_vector(7 downto 0);
    signal  SP, iSP         : std_logic_vector(7 downto 0);
    signal  DPTR0           : std_logic_vector(15 downto 0);    -- DPTR0
    signal  DPTR0_Plus_ACC  : std_logic_vector(15 downto 0);
    ALIAS   DPH0            : std_logic_vector(7 downto 0) is DPTR0(15 downto 8);
    ALIAS   DPL0            : std_logic_vector(7 downto 0) is DPTR0( 7 downto 0);
    signal  DPTR1           : std_logic_vector(15 downto 0);    -- DPTR1
    signal  DPTR1_Plus_ACC  : std_logic_vector(15 downto 0);
    ALIAS   DPH1            : std_logic_vector(7 downto 0) is DPTR1(15 downto 8);
    ALIAS   DPL1            : std_logic_vector(7 downto 0) is DPTR1( 7 downto 0);
    signal  DPS             : std_logic_vector(7 downto 0); -- DPS
    ALIAS   DPS_SEL         : std_logic is DPS(0);
    signal  CKCON           : std_logic_vector(7 downto 0); -- CKCON

    signal  PC              : std_logic_vector(15 downto 0);
    signal  PC_Plus_1, PC_Plus_2, PC_Minus_1,
            PC_Plus_cInst1,
            PC_Plus_cInst2  : std_logic_vector(15 downto 0);
    signal  MPAGE           : std_logic_vector(7 downto 0);

    signal  PCC             : std_logic_vector(15 downto 0);
    signal  nPC             : std_logic_vector(15 downto 0);
    signal  oPC             : std_logic_vector(15 downto 0);

    -- ALU signals
    signal  Op_A            : std_logic_vector(7 downto 0);
    signal  Op_B            : std_logic_vector(7 downto 0);
    signal  Mem_A           : std_logic_vector(7 downto 0);
    signal  Mem_A_Rd        : std_logic;
    signal  Mem_Din         : std_logic_vector(7 downto 0);
    signal  Old_Mem_A       : std_logic_vector(7 downto 0);
    signal  ACC_Q           : std_logic_vector(7 downto 0);
    signal  B_Q             : std_logic_vector(7 downto 0);
    signal  Res_Bus         : std_logic_vector(7 downto 0);
    signal  Status_D        : std_logic_vector(7 downto 5);
    signal  Status_Wr       : std_logic_vector(7 downto 5);

    -- Misc signals
    signal  Int_AddrA       : std_logic_vector(7 downto 0);
    signal  Int_AddrA_r     : std_logic_vector(7 downto 0);
    signal  Last            : std_logic;
    signal  FCycle          : std_logic_vector(1 downto 0);

    signal  RET_r           : std_logic;

    signal  Next_PSW7       : std_logic;
    signal  Next_ACC_Z      : std_logic;
    signal  ACC_Wr          : std_logic;
    signal  B_Wr            : std_logic;

    signal  SFR_RData       : std_logic_vector(7 downto 0);
    signal  SFR_RData_r     : std_logic_vector(7 downto 0);



    signal  Bit_Pattern     : std_logic_vector(7 downto 0);

    -- Registered instruction words.
    signal  cInst           : std_logic_vector(7 downto 0);
    signal  cInst1          : std_logic_vector(7 downto 0);
    signal  cInst2          : std_logic_vector(7 downto 0);
    signal  cInst_MCode     : std_logic_vector(8 downto 0);
    alias   cInst_Length    : std_logic_vector(1 downto 0) is cInst_MCode(1 downto 0);
    alias   nInst           : std_logic_vector(7 downto 0) is ROM_Data;
    alias   nInst_Rn_Index  : std_logic_vector(2 downto 0) is ROM_Data(2 downto 0);
    signal  nInst_MCode     : std_logic_vector(8 downto 0);

    -- Control signals
    signal  RAM_Rd_i        : std_logic;
    signal  RAM_Wr_i        : std_logic;
    signal  Rst_r_n         : std_logic;
    signal  SFR_Rd_i        : std_logic;
    signal  SFR_Wr_i        : std_logic;
    signal  SFR_Wr_p        : std_logic;
    signal  Mem_Wr          : std_logic;
    signal  Mem_Wr_p        : std_logic;
    signal  J_Skip          : boolean;
    signal  IPending        : boolean;
    signal  Int_Trig_r      : std_logic_vector(10 downto 0);
    signal  ICall           : boolean;
    signal  HPInt           : boolean;
    signal  LPInt           : boolean;
    signal  PCPaused        : std_logic_vector(3 downto 0);
    signal  Div_Rdy         : std_logic;
    signal  INC_DPTR        : boolean;
    signal  CJNE            : std_logic;
    signal  DJNZ            : std_logic;

    -- Mux control
    signal  AMux_SFR        : boolean;
    signal  BMux_Inst2      : boolean;
    signal  RMux_PCL        : boolean;
    signal  RMux_PCH        : boolean;

    signal  INT_reject      : boolean;
    signal  First_Cycle, Second_Cycle, Third_Cycle : boolean;
    signal  Last_Cycle      : boolean;
    signal  Inst_Skip       : boolean;
    signal  IStart          : boolean;
    signal  Ri_Stall        : boolean;
    signal  PSW_Stall       : boolean;
    signal  RW_Stall        : boolean;
    signal  PCPause         : boolean;
    signal  Ready           : boolean;
    signal  NOP             : boolean;
    signal  nInst_is_Ri, nInst_is_Rn    : boolean;
    signal  nInst_is_RET, nInst_is_RETI : boolean;
    signal  nInst_is_DR     : boolean;
    signal  cInst_is_DW, cInst_is_MOVX_Write, cInst_is_MOVX_Read,
            cInst_is_RET, cInst_is_RETI, cInst_is_MOVC, cInst_is_DIV,
            cInst_is_PUSH, cInst_is_POP, cInst_is_ACALL, cInst_is_LCALL,
            cInst_is_Ri, cInst_is_Rn, cInst_is_A_Write, cInst_is_MUL,
            cInst_is_INC_DPTR, cInst_is_JC, cInst_is_JNC,
            cInst_is_JZ, cInst_is_JNZ, cInst_is_SJMP, cInst_is_AJMP,
            cInst_is_JB, cInst_is_JNB, cInst_is_JBC, cInst_is_LJMP,
            cInst_is_IW, cInst_is_DR, cInst_is_CJNE, cInst_is_DJNE,
            cInst_is_DJNZ, cInst_is_JMP_A_DPTR, cInst_is_7x, cInst_is_8x,
            cInst_is_Ax, cInst_is_x3, cInst_is_x5
            : boolean;

    signal  EIP       : std_logic_vector(7 downto 0);
    signal  INT_IP    : std_logic_vector(10 downto 0);
    signal  IRQ_Entry : std_logic_vector(15 downto 0);

begin

    ----------------------------------------------------------------------------
    iRAM_Rd    <= Mem_A_Rd;
    iRAM_Wr    <= Mem_Wr;
    iRAM_WData <= Mem_Din;
    iRAM_Addr  <= Int_AddrA_r when Mem_Wr = '1' else Int_AddrA;

    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
			Mem_A <= (others => '0');
        elsif Clk'event and Clk = '1' then
            if Mem_A_Rd = '1' then
                Mem_A <= iRAM_RData;
            end if;
            if Mem_Wr = '1' then
                if Int_AddrA_r = Int_AddrA then
                    Mem_A  <= Mem_Din;
                end if;
            end if;
        end if;
    end process;

    ----------------------------------------------------------------------------
    ROM_Addr <= nPC;
    ----------------------------------------------------------------------------
    -- Ready
    Ready <= (Idle_n = '1');
    ----------------------------------------------------------------------------
    -- Next Instruction is @Ri
    nInst_is_Ri   <= (nInst_MCode(7) = '1');
    nInst_is_Rn   <= (nInst_MCode(8) = '1');
    nInst_is_RET  <= (nInst = "00100010");
    nInst_is_RETI <= (nInst = "00110010");
    nInst_is_DR   <= (nInst_MCode(5) = '1');
    ----------------------------------------------------------------------------
    -- Program counter
    --PC_Plus_1      <= PC + 1;
    --PC_Plus_2      <= PC + 2;
    --PC_Minus_1     <= PC - 1;
    --PC_Plus_cInst1 <= std_logic_vector(conv_unsigned(signed(PC) +
    --                                                       signed(cInst1), 16));
    --PC_Plus_cInst2 <= std_logic_vector(conv_unsigned(signed(PC) +
    --                                                       signed(cInst2), 16));

    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then
            PC          <= (others => '0');
            PC_Plus_1   <= "0000000000000001";
            PC_Plus_2   <= "0000000000000010";
            PC_Minus_1  <= "1111111111111111";
        elsif Clk'event and Clk = '1' then
            if Ready then
                PC          <= nPC;
                PC_Plus_1   <= nPC + 1;
                PC_Plus_2   <= nPC + 2;
                PC_Minus_1  <= nPC - 1;
            end if;
        end if;
    end process;

    -- PC_Plus_cInst1
    process (Rst_n, Clk)
    begin
        if Rst_n = '0' then