it51_top.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

    signal  sfr_CS_Glue : std_logic;
    signal  sfr_rd_i    : std_logic;
    signal  sfr_wr_i    : std_logic;
    signal  sfr_addr_i     : std_logic_vector(6 downto 0);
    signal  sfr_addr_r     : std_logic_vector(6 downto 0);
    signal  sfr_data_out_i : std_logic_vector(7 downto 0);
    signal  sfr_data_in_i    : std_logic_vector(7 downto 0);
    signal  sfr_data_in_Glue : std_logic_vector(7 downto 0);
    signal  sfr_data_in_TC01 : std_logic_vector(7 downto 0);
    signal  sfr_data_in_TC2  : std_logic_vector(7 downto 0);
    signal  sfr_data_in_UART : std_logic_vector(7 downto 0);
    signal  INT0, INT1  : std_logic;
    signal  INT3        : std_logic;
    signal  INT5        : std_logic;
    signal  ROM_Data_r  : std_logic_vector(7 downto 0);
    signal  RAM_Addr_r  : std_logic_vector(15 downto 0);
    signal  core_iRAM_Addr   : std_logic_vector(7 downto 0);
    signal  core_iRAM_Rd     : std_logic;
    signal  core_iRAM_Wr     : std_logic;
    signal  core_iRAM_RData  : std_logic_vector(7 downto 0);
    signal  core_iRAM_WData  : std_logic_vector(7 downto 0);
begin

    INT0     <= int0_n;
    INT1     <= int1_n;
    INT3     <= int3_n;
    INT5     <= int5_n;

    mem_rd_n <= not RAM_RD;
    mem_wr_n <= not RAM_WR;
    mem_addr <= RAM_Addr_r;

    stop_mode_n    <= Stop_n;
    idle_mode_n    <= Idle_n;

    sfr_data_in_i  <= sfr_data_in_Glue when sfr_CS_Glue = '1' else
                      sfr_data_in_TC01 when (TMOD_Sel or TL0_Sel or TL1_Sel or
                                             TH0_Sel or TH1_Sel ) = '1' else
                      sfr_data_in_TC2  when (T2CON_Sel or RCAP2L_Sel or
                                             RCAP2H_Sel or TL2_Sel or
                                             TH2_Sel) = '1' else
                      sfr_data_in_UART when (SCON_Sel or SBUF_Sel)='1' else
                      sfr_data_in;

    sfr_data_out         <= sfr_data_out_i;
    sfr_addr(7)          <= '1';
    sfr_addr(6 downto 0) <= sfr_addr_i;
    sfr_wr               <= sfr_wr_i;
    sfr_rd               <= sfr_rd_i;

    irom_rd_n            <= '0';
    irom_cs_n            <= '0';

    iram_addr            <= core_iRAM_Addr;
    iram_data_in         <= core_iRAM_WData;
    iram_rd_n            <= not core_iRAM_Rd;
    iram_we1_n           <= '1';
    iram_we2_n           <= not core_iRAM_Wr;
    core_iRAM_RData      <= iram_data_out;
  -----------------------------------------------------------
  -- YFC
  -----------------------------------------------------------
  rst_n     <= por_n and por_n_del2;
  rst_out_n <= por_n and por_n_del2;

  por_del_proc: process (clk, Rst_n)
  begin
    if Rst_n = '0' then
        por_n_del1 <= '1';
        por_n_del2 <= '1';
        ROM_Data_r <= (others => '0');
        RAM_Addr_r <= (others => '0');
    elsif (clk'event and clk = '1') then
        por_n_del1 <= por_n;
        por_n_del2 <= por_n_del1;
        ROM_Data_r <= irom_data_out;
        RAM_Addr_r <= RAM_Addr;
    end if;
  end process por_del_proc;

  -----------------------------------------------------------

    process (Clk, Rst_n)
    begin
        if Rst_n = '0' then
            sfr_addr_r <= (others => '0');
        elsif Clk'event and Clk = '1' then
            sfr_addr_r <= sfr_addr_i;
        end if;
    end process;

    core51 : IT51_core
        port map(
            Clk            => Clk,
            Rst_n          => rst_n,
            Idle_n         => Idle_n,
            ROM_Addr       => irom_addr,
            ROM_Data       => ROM_Data_r,
            RAM_Addr       => RAM_Addr,
            RAM_RData      => mem_data_in,
            RAM_WData      => mem_data_out,
            RAM_Cycle      => RAM_Cycle,
            RAM_Rd         => RAM_Rd,
            RAM_Wr         => RAM_Wr,
            iRAM_Addr      => core_iRAM_Addr ,
            iRAM_Rd        => core_iRAM_Rd   ,
            iRAM_Wr        => core_iRAM_Wr   ,
            iRAM_RData     => core_iRAM_RData,
            iRAM_WData     => core_iRAM_WData,
            Int_Trig       => Int_Trig,
            Int_Acc        => Int_Acc,
            SFR_Rd         => sfr_rd_i,
            SFR_Wr         => sfr_wr_i,
            SFR_Addr       => sfr_addr_i,
            SFR_WData      => sfr_data_out_i,
            SFR_RData_Ext  => sfr_data_in_i);

    glue51 : IT51_Glue
        port map(
            Clk        => Clk,
            Rst_n      => Rst_n,

            IO_Wr      => sfr_wr_i,
            IO_Rd      => sfr_rd_i,
            IO_CS      => sfr_CS_Glue,
            IO_Addr    => sfr_addr_i,
            IO_Addr_r  => sfr_addr_r,
            IO_WData   => sfr_data_out_i,
            IO_RData   => sfr_data_in_Glue,

            INT0       => INT0,
            INT1       => INT1,
            INT2       => INT2,
            INT3       => INT3,
            INT4       => INT4,
            INT5       => INT5,

            RI         => RI,
            TI         => TI,
            OF0        => OF0,
            OF1        => OF1,
            OF2        => OF2,

            Int_Acc    => Int_Acc,
            R0         => R0,
            R1         => R1,
            SMOD       => SMOD,
            TMOD_Sel   => TMOD_Sel,
            TL0_Sel    => TL0_Sel,
            TL1_Sel    => TL1_Sel,
            TH0_Sel    => TH0_Sel,
            TH1_Sel    => TH1_Sel,
            T2CON_Sel  => T2CON_Sel,
            RCAP2L_Sel =>RCAP2L_Sel,
            RCAP2H_Sel => RCAP2H_Sel,
            TL2_Sel    => TL2_Sel,
            TH2_Sel    => TH2_Sel,
            SCON_Sel   => SCON_Sel,
            SBUF_Sel   => SBUF_Sel,
            TMOD_Wr    => TMOD_Wr,
            TL0_Wr     => TL0_Wr,
            TL1_Wr     => TL1_Wr,
            TH0_Wr     => TH0_Wr,
            TH1_Wr     => TH1_Wr,
            T2CON_Wr   => T2CON_Wr,
            RCAP2L_Wr  => RCAP2L_Wr,
            RCAP2H_Wr  => RCAP2H_Wr,
            TL2_Wr     => TL2_Wr,
            TH2_Wr     => TH2_Wr,
            SCON_Wr    => SCON_Wr,
            SBUF_Wr    => SBUF_Wr,
            Int_Trig   => Int_Trig,
            Idle_n     => Idle_n,
            Stop_n     => Stop_n);

    tc01 : IT51_TC01
        port map(
            Clk      => Clk,
            Rst_n    => Rst_n,
            T0       => T0,
            T1       => T1,
            INT0     => int0_n,
            INT1     => int1_n,
            M_Sel    => TMOD_Sel,
            H0_Sel   => TH0_Sel,
            L0_Sel   => TL0_Sel,
            H1_Sel   => TH1_Sel,
            L1_Sel   => TL1_Sel,
            R0       => R0,
            R1       => R1,
            M_Wr     => TMOD_Wr,
            H0_Wr    => TH0_Wr,
            L0_Wr    => TL0_Wr,
            H1_Wr    => TH1_Wr,
            L1_Wr    => TL1_Wr,
            Data_In  => sfr_data_out_i,
            Data_Out => sfr_data_in_TC01,
            OF0      => OF0,
            OF1      => OF1);

    tc2 : IT51_TC2
        port map(
            Clk      => Clk,
            Rst_n    => Rst_n,
            T2       => T2,
            T2EX     => T2EX,
            C_Sel    => T2CON_Sel,
            CH_Sel   => RCAP2H_Sel,
            CL_Sel   => RCAP2L_Sel,
            H_Sel    => TH2_Sel,
            L_Sel    => TL2_Sel,
            C_Wr     => T2CON_Wr,
            CH_Wr    => RCAP2H_Wr,
            CL_Wr    => RCAP2L_Wr,
            H_Wr     => TH2_Wr,
            L_Wr     => TL2_Wr,
            Data_In  => sfr_data_out_i,
            Data_Out => sfr_data_in_TC2,
            UseR2    => UseR2,
            UseT2    => UseT2,
            UART_Clk => UART_Clk,
            F        => OF2);

    uart : IT51_UART
        port map(
            Clk      => Clk,
            Rst_n    => Rst_n,
            UseR2    => UseR2,
            UseT2    => UseT2,
            BaudC2   => UART_Clk,
            BaudC1   => OF1,
            SC_Sel   => SCON_Sel,
            SB_Sel   => SBUF_Sel,
            SC_Wr    => SCON_Wr,
            SB_Wr    => SBUF_Wr,
            SMOD     => SMOD,
            Data_In  => sfr_data_out_i,
            Data_Out => sfr_data_in_UART,
            RXD      => rxd0_in,
--          RXD_IsO  => RXD_IsO,
            RXD_O    => rxd0_out,
            TXD      => txd0,
            RI       => RI,
            TI       => TI);

end;