it51_top.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

-------------------------------------------------------------------------------
--   IT51 (Improved-T51)                                                     --
--                                                                           --
--   VERSION: 030723                                                         --
--                                                                           --
--   Contact: [e-mail]                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
--  Copyright (c) 2001-2002 Daniel Wallner ([e-mail])             --
--                          Yung-Fu Chen ([e-mail])           --
--                                                                           --
-------------------------------------------------------------------------------
--  FETURE                                                                   --
--     . IT51_top interface is similar to synopsys DW8051                    --
--     . High-Performance 1-Cycle 8051                                       --
--     . instruction compatible with standard DW8051                         --
--     . 256 byte internal data memory                                       --
--     . up to 64KB external data memory                                     --
--     . up to 64KB internal program memory                                  --
--     . export sfr-bus                                                      --
--     . no dual-port memory used                                            --
--     . no watch-dog timer                                                  --
--     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
--     . sleep mode support, refer to DW8051                                 --
--     . no stop mode                                                        --
--     . six external interrupt, refer to DW8051                             --
--     . pass all DW8051 test-pattern                                        --
--     . UART/Timer are not fully tested yet                                 --
--     . no internal tri-state bus                                           --
--     . 2-Cycle MUL Instruction                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51_top (Interface Compatible with Synopsys DW8051)                     --
--     |                                                                     --
--     +-- IT51_core (Control Unit)                                          --
--     |       |                                                             --
--     |       +-- IT51_ALU (ALU)                                            --
--     |               |                                                     --
--     |               +-- IT51_MD (MUL/DIV)                                 --
--     |                                                                     --
--     +-- IT51_Glue (Glue Logic)                                            --
--     |                                                                     --
--     +-- IT51_TC01 (Timer/Counter-1)                                       --
--     |                                                                     --
--     +-- IT51_TC2 (Timer/Counter-2)                                        --
--     |                                                                     --
--     +-- IT51_UART (UART)                                                  --
--                                                                           --
-------------------------------------------------------------------------------

-- ============================================================================
-- The original T51 license is listed below:
-- ============================================================================
--
-- 8051 compatible microcontroller core
--
-- Version : 0218
--
-- Copyright (c) 2001-2002 Daniel Wallner ([e-mail])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--	http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- ============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

library work;
use work.IT51_Pack.all;

entity IT51_top is
    port (
        -- internal interface:
        clk             : in  std_Logic;
        por_n           : in  std_logic;
        rst_out_n       : out std_logic;

        stop_mode_n     : out std_logic;
        idle_mode_n     : out std_logic;

        sfr_addr        : out std_logic_vector (7 downto 0);
        sfr_data_out    : out std_logic_vector (7 downto 0);
        sfr_data_in     : in  std_logic_vector (7 downto 0);
        sfr_wr          : out std_logic;
        sfr_rd          : out std_logic;

        int0_n          : in  std_logic;        -- External Interrupt 0
        int1_n          : in  std_logic;        -- External Interrupt 1
        int2            : in  std_logic;        -- External Interrupt 2
        int3_n          : in  std_logic;        -- External Interrupt 3
        int4            : in  std_logic;        -- External Interrupt 4
        int5_n          : in  std_logic;        -- External Interrupt 5

        rxd0_in         : in  std_logic;        -- serial port0 input
        rxd0_out        : out std_logic;        -- serial port0 output
        txd0            : out std_logic;        -- serial port0 output
        rxd1_in         : in  std_logic;        -- serial port1 input
        rxd1_out        : out std_logic;        -- serial port1 output
        txd1            : out std_logic;        -- serial port1 output

        t0              : in  std_logic;        -- Timer 0 external input
        t1              : in  std_logic;        -- Timer 1 external input

        t2              : in  std_logic;        -- Timer/Counter2 ext.input
        t2ex            : in  std_logic;        -- Timer/Counter2 capt./reload

        t0_out          : out std_logic;        -- Timer/Counter0 overflow
        t1_out          : out std_logic;        -- Timer/Counter1 overflow
        t2_out          : out std_logic;        -- Timer/Counter2 overflow

        -- external interface:
        mem_addr        : out std_logic_vector (15 downto 0);
        mem_data_out    : out std_logic_vector (7 downto 0);
        mem_data_in     : in  std_logic_vector (7 downto 0);
        mem_wr_n        : out std_logic;
        mem_rd_n        : out std_logic;

        iram_addr       : out std_logic_vector (7 downto 0);
        iram_data_out   : in  std_logic_vector (7 downto 0);
        iram_data_in    : out std_logic_vector (7 downto 0);
        iram_rd_n       : out std_logic;
        iram_we1_n      : out std_logic;
        iram_we2_n      : out std_logic;

        irom_addr       : out std_logic_vector (15 downto 0);
        irom_data_out   : in  std_logic_vector (7 downto 0);
        irom_rd_n       : out std_logic;
        irom_cs_n       : out std_logic
       );

end IT51_top;

architecture rtl of IT51_top is

    signal  Idle_n      : std_logic;
    signal  Stop_n      : std_logic;
    signal  ROM_Addr    : std_logic_vector(15 downto 0);
    signal  ROM_Data    : std_logic_vector(7 downto 0);
    signal  RAM_Addr    : std_logic_vector(15 downto 0);
    signal  RAM_RData   : std_logic_vector(7 downto 0);
    signal  RAM_DO      : std_logic_vector(7 downto 0);
    signal  RAM_WData   : std_logic_vector(7 downto 0);
    signal  RAM_Rd      : std_logic;
    signal  RAM_Wr      : std_logic;
    signal  RAM_WE_n    : std_logic;
    signal  RAM_Sel_n   : std_logic;
    signal  Ex_Sel_i    : std_logic;
    signal  IO_Rd       : std_logic;
    signal  IO_Wr       : std_logic;
    signal  IO_Addr     : std_logic_vector(6 downto 0);
    signal  IO_Addr_r   : std_logic_vector(6 downto 0);
    signal  IO_WData    : std_logic_vector(7 downto 0);
    signal  IO_RData    : std_logic_vector(7 downto 0);

    signal  P0_Sel      : std_logic;
    signal  P1_Sel      : std_logic;
    signal  P2_Sel      : std_logic;
    signal  P3_Sel      : std_logic;
    signal  TMOD_Sel    : std_logic;
    signal  TL0_Sel     : std_logic;
    signal  TL1_Sel     : std_logic;
    signal  TH0_Sel     : std_logic;
    signal  TH1_Sel     : std_logic;
    signal  T2CON_Sel   : std_logic;
    signal  RCAP2L_Sel  : std_logic;
    signal  RCAP2H_Sel  : std_logic;
    signal  TL2_Sel     : std_logic;
    signal  TH2_Sel     : std_logic;
    signal  SCON_Sel    : std_logic;
    signal  SBUF_Sel    : std_logic;

    signal  P0_Wr       : std_logic;
    signal  P1_Wr       : std_logic;
    signal  P2_Wr       : std_logic;
    signal  P3_Wr       : std_logic;
    signal  TMOD_Wr     : std_logic;
    signal  TL0_Wr      : std_logic;
    signal  TL1_Wr      : std_logic;
    signal  TH0_Wr      : std_logic;
    signal  TH1_Wr      : std_logic;
    signal  T2CON_Wr    : std_logic;
    signal  RCAP2L_Wr   : std_logic;
    signal  RCAP2H_Wr   : std_logic;
    signal  TL2_Wr      : std_logic;
    signal  TH2_Wr      : std_logic;
    signal  SCON_Wr     : std_logic;
    signal  SBUF_Wr     : std_logic;

    signal  UseR2       : std_logic;
    signal  UseT2       : std_logic;
    signal  UART_Clk    : std_logic;
    signal  R0          : std_logic;
    signal  R1          : std_logic;
    signal  SMOD        : std_logic;

    signal  Int_Trig    : std_logic_vector(10 downto 0);
    signal  Int_Acc     : std_logic_vector(10 downto 0);

    signal  RI          : std_logic;
    signal  TI          : std_logic;
    signal  OF0         : std_logic;
    signal  OF1         : std_logic;
    signal  OF2         : std_logic;
-- YFC
    signal  RAM_Cycle   : std_logic;
    signal  rst_n       : std_logic;
    signal  por_n_del1  : std_logic;
    signal  por_n_del2  : std_logic;