it51_alu.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

-------------------------------------------------------------------------------
--   IT51 (Improved-T51)                                                     --
--                                                                           --
--   VERSION: 030723                                                         --
--                                                                           --
--   Contact: [e-mail]                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
--  Copyright (c) 2001-2002 Daniel Wallner ([e-mail])             --
--                          Yung-Fu Chen ([e-mail])           --
--                                                                           --
-------------------------------------------------------------------------------
--  FETURE                                                                   --
--     . IT51_top interface is similar to synopsys DW8051                    --
--     . High-Performance 1-Cycle 8051                                       --
--     . instruction compatible with standard DW8051                         --
--     . 256 byte internal data memory                                       --
--     . up to 64KB external data memory                                     --
--     . up to 64KB internal program memory                                  --
--     . export sfr-bus                                                      --
--     . no dual-port memory used                                            --
--     . no watch-dog timer                                                  --
--     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
--     . sleep mode support, refer to DW8051                                 --
--     . no stop mode                                                        --
--     . six external interrupt, refer to DW8051                             --
--     . pass all DW8051 test-pattern                                        --
--     . UART/Timer are not fully tested yet                                 --
--     . no internal tri-state bus                                           --
--     . 2-Cycle MUL Instruction                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51_top (Interface Compatible with Synopsys DW8051)                     --
--     |                                                                     --
--     +-- IT51_core (Control Unit)                                          --
--     |       |                                                             --
--     |       +-- IT51_ALU (ALU)                                            --
--     |               |                                                     --
--     |               +-- IT51_MD (MUL/DIV)                                 --
--     |                                                                     --
--     +-- IT51_Glue (Glue Logic)                                            --
--     |                                                                     --
--     +-- IT51_TC01 (Timer/Counter-1)                                       --
--     |                                                                     --
--     +-- IT51_TC2 (Timer/Counter-2)                                        --
--     |                                                                     --
--     +-- IT51_UART (UART)                                                  --
--                                                                           --
-------------------------------------------------------------------------------

-- ============================================================================
-- The original T51 license is listed below:
-- ============================================================================
--
-- 8051 compatible microcontroller core
--
-- Version : 0218
--
-- Copyright (c) 2001-2002 Daniel Wallner ([e-mail])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--	http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- ============================================================================

library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.IT51_Pack.all;

entity IT51_ALU is
	port(
		Clk			: in std_logic;
		Rst_n       : in std_logic;
		Last		: in std_logic;
		PCPause     : in boolean;
		OpCode		: in std_logic_vector(7 downto 0);
		ACC			: in std_logic_vector(7 downto 0);
		B			: in std_logic_vector(7 downto 0);
		IA			: in std_logic_vector(7 downto 0);
		IB			: in std_logic_vector(7 downto 0);
		Bit_Pattern	: in std_logic_vector(7 downto 0);
		CY_In		: in std_logic;
		AC_In		: in std_logic;
		ACC_Q		: out std_logic_vector(7 downto 0);
		B_Q			: out std_logic_vector(7 downto 0);
		IDCPBL_Q	: out std_logic_vector(7 downto 0);
		Div_Rdy		: out std_logic;
		CJNE		: out std_logic;
		DJNZ		: out std_logic;
		CY_Out		: out std_logic;
		AC_Out		: out std_logic;
		OV_Out		: out std_logic;
		CY_Wr		: out std_logic;
		AC_Wr		: out std_logic;
		OV_Wr		: out std_logic
	);
end IT51_ALU;

architecture rtl of IT51_ALU is

	signal	Do_A_Imm	: std_logic;
	signal	Do_A_Carry	: std_logic;
	signal	Do_A_RR		: std_logic;
	signal	Do_A_INC	: std_logic;
	signal	Do_A_RRC	: std_logic;
	signal	Do_A_DEC	: std_logic;
	signal	Do_A_RL		: std_logic;
	signal	Do_A_ADD	: std_logic;
	signal	Do_A_RLC	: std_logic;
	signal	Do_A_ORL	: std_logic;
	signal	Do_A_ANL	: std_logic;
	signal	Do_A_XRL	: std_logic;
	signal	Do_A_MOV	: std_logic;
	signal	Do_A_DIV	: std_logic;
	signal	Do_A_SUBB	: std_logic;
	signal	Do_A_MUL	: std_logic;
	signal	Do_A_CJNE 	: std_logic;
	signal	Do_A_SWAP	: std_logic;
	signal	Do_A_XCH	: std_logic;
	signal	Do_A_DA		: std_logic;
	signal	Do_A_XCHD	: std_logic;
	signal	Do_A_CLR	: std_logic;
	signal	Do_A_CPL	: std_logic;

	-- Accumulator ALU input mux
	signal	AOP2		: std_logic_vector(7 downto 0);

	-- AD intermediate signal
	signal	ADA			: std_logic_vector(8 downto 0);

	-- AddSub intermediate signals
	signal	AS_Carry7	: std_logic;
	signal	AS_AC		: std_logic;
	signal	AS_CY		: std_logic;
	signal	AS_Q		: std_logic_vector(7 downto 0);

	signal	Do_I_Imm	: std_logic;
	signal	Do_I_INC	: std_logic;
	signal	Do_I_DEC	: std_logic;
	signal	Do_I_ORL	: std_logic;
	signal	Do_I_ANL	: std_logic;
	signal	Do_I_XRL	: std_logic;
	signal	Do_I_MOV	: std_logic;
	signal	Do_I_MOVD	: std_logic;
	signal	Do_I_CJNE	: std_logic;

	-- Auxiliary ALU input mux
	signal	IOP			: std_logic_vector(7 downto 0);

	-- Auxiliary ALU delayed input
	signal	IA_d		: std_logic_vector(7 downto 0);

	-- AddSub intermediate signals
	signal	CJNE_CY_n	: std_logic;
	signal	CJNE_Q		: std_logic_vector(7 downto 0);

	-- MOV intermediate signals
	signal	MOV_Op		: std_logic_vector(3 downto 0);
	signal	MOV_Q		: std_logic_vector(7 downto 0);

	signal	Do_B_Inv	: std_logic;
	signal	Do_B_C_BA	: std_logic;
	signal	Do_B_C_Dir	: std_logic;
	signal	Do_B_BA_Dir	: std_logic;
	signal	Do_B_MOV	: std_logic;
	signal	Do_B_JBC	: std_logic;
	signal	Do_B_Op		: std_logic_vector(1 downto 0);

	-- Bit intermediate signals
	signal	Bit_Op1		: std_logic_vector(7 downto 0);
	signal	Bit_Op2		: std_logic_vector(7 downto 0);
	signal	Bit_IsOne	: std_logic;
	signal	Bit_Result	: std_logic_vector(7 downto 0);

	signal	Last_r		: std_logic;

	-- MulDiv intermediate signals
	signal	Mul_Q		: std_logic_vector(15 downto 0);
	signal	Mul_OV		: std_logic;
	signal	Div_Q		: std_logic_vector(15 downto 0);
	signal	Div_OV		: std_logic;

	--
	signal  ACC_Q_0     : std_logic_vector(7 downto 0);
	signal  ACC_Q_1     : std_logic_vector(7 downto 0);
	signal  ACC_Q_2     : std_logic_vector(7 downto 0);
	signal  ACC_Q_3     : std_logic_vector(7 downto 0);
	signal  ACC_Q_4     : std_logic_vector(7 downto 0);
	signal  ACC_Q_5     : std_logic_vector(7 downto 0);
	signal  ACC_Q_6     : std_logic_vector(7 downto 0);
	signal  ACC_Q_7     : std_logic_vector(7 downto 0);
	signal  ACC_Q_8     : std_logic_vector(7 downto 0);
	signal  ACC_Q_9     : std_logic_vector(7 downto 0);
	signal  ACC_Q_10    : std_logic_vector(7 downto 0);
	signal  ACC_Q_11    : std_logic_vector(7 downto 0);
	signal  ACC_Q_12    : std_logic_vector(7 downto 0);
	signal  ACC_Q_13    : std_logic_vector(7 downto 0);
    signal  ACC_Q_14    : std_logic_vector(7 downto 0);
    signal  ACC_Q_15    : std_logic_vector(7 downto 0);
    signal  ACC_Q_16    : std_logic_vector(7 downto 0);
    signal  ACC_Q_17    : std_logic_vector(7 downto 0);
    signal  ACC_Q_18    : std_logic_vector(7 downto 0);
    signal  ACC_Q_19    : std_logic_vector(7 downto 0);

begin

	-- Simplify some of the conditions, not all must be exclusive !!!!

	process (Clk, Rst_n)
	begin
	    if Rst_n = '0' then
	        Do_A_Imm    <= '0';
			Do_A_Carry  <= '0';
			Do_A_RR     <= '0';
			Do_A_INC    <= '0';
			Do_A_RRC    <= '0';
			Do_A_DEC    <= '0';
			Do_A_RL     <= '0';
			Do_A_ADD    <= '0';
			Do_A_RLC    <= '0';
			Do_A_ORL    <= '0';
			Do_A_ANL    <= '0';
			Do_A_XRL    <= '0';
			Do_A_MOV    <= '0';
			Do_A_DIV    <= '0';
			Do_A_SUBB   <= '0';
			Do_A_MUL    <= '0';
			Do_A_CJNE   <= '0';
			Do_A_SWAP   <= '0';
			Do_A_XCH    <= '0';
			Do_A_DA     <= '0';
			Do_A_XCHD   <= '0';
			Do_A_CLR    <= '0';
			Do_A_CPL    <= '0';
			Do_A_Imm    <= '0';
			Do_I_Imm    <= '0';
			Do_I_INC    <= '0';
			Do_I_DEC    <= '0';
			Do_I_ORL    <= '0';
			Do_I_ANL    <= '0';
			Do_I_XRL    <= '0';
			Do_I_MOV    <= '0';
			Do_I_MOVD   <= '0';
			Do_I_CJNE   <= '0';
			IA_d        <= (others => '0');
			MOV_Op      <= (others => '0');
			Do_B_Inv    <= '0';
			Do_B_C_BA   <= '0';
			Do_B_C_Dir  <= '0';
			Do_B_BA_Dir <= '0';
			Do_B_MOV    <= '0';
			Do_B_JBC    <= '0';
			Do_B_Op     <= (others => '0');
			Last_r      <= '0';
		elsif Clk'event and Clk = '1' then