it51_md.vhd

這是最新版本修正過後的8051,經過debug並有實現在某家公司的silicon上ㄛ

-------------------------------------------------------------------------------
--   IT51 (Improved-T51)                                                     --
--                                                                           --
--   VERSION: 030723                                                         --
--                                                                           --
--   Contact: [e-mail]                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
--  Copyright (c) 2001-2002 Daniel Wallner ([e-mail])             --
--                          Yung-Fu Chen ([e-mail])           --
--                                                                           --
-------------------------------------------------------------------------------
--  FETURE                                                                   --
--     . IT51_top interface is similar to synopsys DW8051                    --
--     . High-Performance 1-Cycle 8051                                       --
--     . instruction compatible with standard DW8051                         --
--     . 256 byte internal data memory                                       --
--     . up to 64KB external data memory                                     --
--     . up to 64KB internal program memory                                  --
--     . export sfr-bus                                                      --
--     . no dual-port memory used                                            --
--     . no watch-dog timer                                                  --
--     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
--     . sleep mode support, refer to DW8051                                 --
--     . no stop mode                                                        --
--     . six external interrupt, refer to DW8051                             --
--     . pass all DW8051 test-pattern                                        --
--     . UART/Timer are not fully tested yet                                 --
--     . no internal tri-state bus                                           --
--     . 2-Cycle MUL Instruction                                             --
--                                                                           --
-------------------------------------------------------------------------------
--                                                                           --
--  IT51_top (Interface Compatible with Synopsys DW8051)                     --
--     |                                                                     --
--     +-- IT51_core (Control Unit)                                          --
--     |       |                                                             --
--     |       +-- IT51_ALU (ALU)                                            --
--     |               |                                                     --
--     |               +-- IT51_MD (MUL/DIV)                                 --
--     |                                                                     --
--     +-- IT51_Glue (Glue Logic)                                            --
--     |                                                                     --
--     +-- IT51_TC01 (Timer/Counter-1)                                       --
--     |                                                                     --
--     +-- IT51_TC2 (Timer/Counter-2)                                        --
--     |                                                                     --
--     +-- IT51_UART (UART)                                                  --
--                                                                           --
-------------------------------------------------------------------------------

-- ============================================================================
-- The original T51 license is listed below:
-- ============================================================================
--
-- 8051 compatible microcontroller core
--
-- Version : 0218
--
-- Copyright (c) 2001-2002 Daniel Wallner ([e-mail])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
--	http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- ============================================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library work;
use work.IT51_Pack.all;

entity IT51_MD is
	port(
		Clk			: in std_logic;
		Rst_n       : in std_logic;
		ACC			: in std_logic_vector(7 downto 0);
		B			: in std_logic_vector(7 downto 0);
		Mul_Q		: out std_logic_vector(15 downto 0);
		Mul_OV		: out std_logic;
		Div_Q		: out std_logic_vector(15 downto 0);
		Div_OV		: out std_logic;
		Div_Rdy		: out std_logic
	);
end IT51_MD;

architecture rtl of IT51_MD is

	signal Old_ACC	: std_logic_vector(7 downto 0);
	signal Old_B	: std_logic_vector(7 downto 0);
-- YFC
    signal Cnt      : std_logic_vector(3 downto 0);
begin

    process (Clk, Rst_n)
    begin
	    if Rst_n = '0' then
	        Cnt <= (others => '0');
		elsif Clk'event and Clk = '1' then
		    if Old_ACC /= ACC or Old_B /= B then
				Cnt <= "0000";
			else
				Cnt <= Cnt + 1;
			end if;
		end if;
    end process;

	process (ACC, B)
		variable Tmp : std_logic_vector(15 downto 0);
	begin
		Tmp := unsigned(ACC) * unsigned(B);
		Mul_Q <= Tmp;
		if Tmp(15 downto 8) = "00000000" then
			Mul_OV <= '0';
		else
			Mul_OV <= '1';
		end if;
	end process;

	process (Clk, Rst_n)
		variable Tmp1	: unsigned(15 downto 0);
		variable Tmp2	: unsigned(8 downto 0);
		variable Tmp3	: unsigned(8 downto 0);
-- YFC
--		variable Cnt	: unsigned(3 downto 0);
	begin
	    if Rst_n = '0' then
	        Old_ACC <= (others => '0');
			Old_B   <= (others => '0');
			Div_Rdy <= '0';
			Div_OV  <= '0';
			Div_Q   <= (others => '0');
			Tmp1    := (others => '0');
			Tmp3    := (others => '0');
		elsif Clk'event and Clk = '1' then
			Old_ACC <= ACC;
			Old_B <= B;
			Div_Rdy <= '0';
			Div_OV <= '0';

			if Cnt(3) = '1' then
				Div_Rdy <= '1';
			end if;

            if B = "00000000" then
-- YFC >>>
-- BUG (op_84)
				Div_Q ( 7 downto 0) <= (others => '1');
				Div_Q (15 downto 8) <= std_logic_vector(ACC);
				Div_OV <= '1';
				Div_Rdy <= '1';
--- <<<
			elsif ACC = B then
				Div_Q(7 downto 0) <= "00000001";
				Div_Q(15 downto 8) <= "00000000";
			elsif ACC < B then
				Div_Q(7 downto 0) <= "00000000";
				Div_Q(15 downto 8) <= std_logic_vector(ACC);
				Div_Rdy <= '1';
			elsif Cnt(3) = '0' then
				Tmp1(15 downto 1) := Tmp1(14 downto 0);
				Tmp1(0) := '0';
				Tmp2 := ("1" & Tmp1(15 downto 8)) - Tmp3;
				if Tmp2(8) = '1' then
					Tmp1(0) := '1';
					Tmp1(15 downto 8) := Tmp2(7 downto 0);
				end if;
				Div_Q <= std_logic_Vector(Tmp1);
			end if;

			if Old_ACC /= ACC or Old_B /= B then
				Tmp1(7 downto 0) := unsigned(ACC);
				Tmp1(15 downto 8) := "00000000";
--				Tmp3 := "0" & unsigned(B);
				Tmp3 := unsigned("0" & B);
-- YFC
--				Cnt := "0000";

				Div_Rdy <= '0';
--			else
--				cnt := cnt + 1;
			end if;

		end if;
	end process;

end;