quickhdl.ini

這是Originl公司出的8051 VHDL source code.

[Library]
others = /mgc.B.4/lib/quickhdl.ini
work   = $HOME/8051/work
mc8051 = $HOME/8051ren/src/mc8051


[vsim]
main_window_pos = 88 267 598 292
signal_window_pos = 108 81 273 656
wave_window_pos = 18 51 1024 859
structure_window_pos = 11 802 252 372
source_window_pos = 201 377 667 405
variable_window_pos = 500 359 483 345
process_window_pos = 345 16 335 277
list_window_pos = 132 108 793 702
df_window_pos = 373 564 503 464
; Dynamically linked object containing user's
; Verilog PLI tasks and functions.
; Veriuser = veriuser.o

; Default run length
RunLength = 100

; Iterations that can be run without advancing simulation time
IterationLimit = 5000

; Simulator resolution
Resolution = ps

; Stop the simulator after an assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; List Translation
; Map an enumerated value to 0, 1, or Z.  Default is 'X';
List0 = '0' FALSE 'L' s0r s0s
List1 = '1' TRUE 'H' s1r s1s
ListZ = 'Z' sxz s0z s1z
listX = sxr sxz sxs sxi s0i s1i

; Force Translation
; Map 1s and 0s to the enumerated value
Force0 = '0' FALSE s0s
Force1 = '1' TRUE s1s

; Default radix for all windows and commands...
; 0 = symbolic, 2 = binary, 8 = octal, 10 = decimal, 16 = hex
DefaultRadix = 0

; This controls the number of characters of a signal name
; shown in the waveform window. The default value or a
; value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 10

; QHSIM Startup command
; Startup = do startup.do

; Save the command window contents to this file
; TranscriptFile = transcript

; Disable assertion messages
; ignoreNote = 1
; ignoreWarning = 1
; ignoreError = 1
; ignoreFailure = 1

; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0

; window positions
; Position values correspond as given below
; window_name_pos = y_position x_position width height
schematic_window_pos = 0 539 603 299

; List of object libraries to search for C interface
ForeignLibs = /usr/lib/libc.a

; Delay opening of files until first read or write. (enable=1)
DelayFileOpen = 0

[lmc]
; QuickHDL's interface to SWIFT software
libsm = $MGC_HOME/pkgs/quickhdl/.lib/libsm.sl
; Logic Modeling's SWIFT software (Sun Solaris)
libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so


; Note: See Synopsis documentation on how to install
;       the hardware modeler's SFI software. Modify
;       the below given libsfi definition to incorporate
;       the hardware modeler's installation path.
;
;libsfi = <install_dir>/sms/lib/sun4.solaris/libsfi.so
;
; QHSIM's hardware modeler interface to SFI software
libhm = $MGC_HOME/pkgs/quickhdl/.lib/libhm.sl