p3_drv_spec.vhd

這是Originl公司出的8051 VHDL source code.

--------------------------------------------------
-- Model        :   8051 Behavioral Model,
--                  VHDL Entity mc8051.p3_drv.interface
--
-- Author       :   Michael Mayer ([e-mail]),
--                  Dr. Hardy J. Pottinger,
--                  Department of Electrical Engineering
--                  University of Missouri - Rolla
--
-- Created at   :   09/22/98 19:32:41
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY mc8051 ;
USE mc8051.synth_pack.all;

ENTITY p3_drv IS
   PORT( 
      addr_gb : IN     std_logic_vector( 7 DOWNTO 0 )  ;
      indirect_sel : IN     std_logic ;
      int_clk : IN     std_logic ;
      int_rst : IN     std_logic ;
      latch_pins : IN     std_logic ;
      rd_gb : IN     std_logic ;
      rd_n : IN     std_logic ;
      rd_n_ctrl : IN     std_logic ;
      read_latch : IN     std_logic ;
      rxd_ctrl : IN     std_logic ;
      txd : IN     std_logic ;
      txd_ctrl : IN     std_logic ;
      wr_gb : IN     std_logic ;
      wr_n : IN     std_logic ;
      wr_n_ctrl : IN     std_logic ;
      acknow : OUT    std_logic ;
      rxd : OUT    std_logic ;
      P3 : INOUT  std_logic_vector( 7 DOWNTO 0 )  ;
      data_gb : INOUT  std_logic_vector( 7 DOWNTO 0 ) 
   );

-- Declarations

END p3_drv ;
--
-- VHDL Architecture mc8051.p3_drv.spec
--
-- Created:
--          by - mrmayer.UNKNOWN (eceultra20.ece.umr.edu)
--          at - 19:52:48 09/19/98
--
-- Generated by Mentor Graphics' Renoir(TM) 3.4 (Build 18)
--
architecture spec of p3_drv is
    SIGNAL  p3_reg   : bvec := "00000000";
    SIGNAL  p3_sel   : std_logic;

begin
    -- The p3 is selected by addr B0 and NOT indirect_sel
    p3_sel <= '1' WHEN (addr_gb = "10110000") AND (indirect_sel = '0') ELSE
              '0';
 
    -- The p3 is reset to 1's during reset,
    -- set to the data_gb during a write to p3, or else left alone.
    p3_reg <= "11111111" WHEN int_rst = '1' ELSE                 -- reset
               unsigned(data_gb)   WHEN (wr_gb = '1' AND p3_sel = '1') ELSE -- async
               p3_reg;
 
    p3 <= std_logic_vector(to_high_imped(p3_reg));

    rxd <= p3(0);
    P3(1)  <= txd     WHEN txd_ctrl  = '1' ELSE 'Z';
    --P3(2)  <= int0_n  WHEN int0_ctrl = '1' ELSE 'Z';
    --P3(3)  <= int1_n  WHEN int1_ctrl = '1' ELSE 'Z';
    --P3(4)  <= t0      WHEN t0_ctrl   = '1' ELSE 'Z';
    --P3(5)  <= t1      WHEN t1_ctrl   = '1' ELSE 'Z';
    P3(6)  <= wr_n    WHEN wr_n_ctrl = '1' ELSE 'Z';
    P3(7)  <= rd_n    WHEN rd_n_ctrl = '1' ELSE 'Z';

 
    -- The data_gb is driven with the p3_ref during a read from p3_reg,
    -- or else left in high impedance.
    data_gb <= to_x01(p3) WHEN rd_gb = '1' AND p3_sel = '1' AND read_latch = '0' ELSE
               std_logic_vector(p3_reg)    WHEN rd_gb = '1' AND p3_sel = '1' AND read_latch = '1' ELSE
               "ZZZZZZZZ";
 
    -- The acknowledge is pulled high when the global bus and p3
    -- reg become equal (considered stable) and the p3 is selected.
    acknow <= '1' WHEN data_gb = std_logic_vector(p3_reg) AND p3_sel = '1' ELSE
              'Z';
 
end spec;